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1. 发明授权

US4772566A Single tub transistor means and method 失效
标题翻译：单桶晶体管的手段和方法
公开(公告)号：US4772566A
公开(公告)日：1988-09-20
申请号：US68373
申请日：1987-07-01
申请人： Peter J. Zdebel , Bor-Yuan Hwang , Allen J. Wagner
发明人： Peter J. Zdebel , Bor-Yuan Hwang , Allen J. Wagner
IPC分类号： H01L29/73 , H01L21/28 , H01L21/285 , H01L21/331 , H01L21/60 , H01L29/732 , H01L21/225 , H01L21/20
CPC分类号： H01L21/76897 , H01L21/28525 , H01L29/66272
摘要： A means and method for forming a single tub transistor, such as for example a vertical NPN bipolar transistor surrounded by an isolation wall, is described. Multiple polysilicon and dielectric layers are employed in conjunction with a master mask and with isotropic and anisotropic etching procedures to define the contacts and active regions of the device without resorting to precision alignments. Sub-micron lateral device contacts are easily achieved even with comparatively coarse lithographic methods through use of sidewall spacers for controlled narrowing of critical device openings. The finished device is especially compact, has low resistance contacts for its size, and provides very high speed operation.

2. 发明授权

US5067002A Integrated circuit structures having polycrystalline electrode contacts 失效
标题翻译：具有多晶电极触点的集成电路结构
公开(公告)号：US5067002A
公开(公告)日：1991-11-19
申请号：US304984
申请日：1989-01-31
申请人： Peter J. Zdebel , Raymond J. Balda , Bor-Yuan Hwang , Allen J. Wagner
发明人： Peter J. Zdebel , Raymond J. Balda , Bor-Yuan Hwang , Allen J. Wagner
IPC分类号： H01L21/033 , H01L21/225 , H01L21/285
CPC分类号： H01L21/033 , H01L21/2257 , H01L21/28525
摘要： A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.
摘要翻译：公开了一种用于制造改进的集成电路器件的工艺。根据本发明的一个实施例，通过在不依赖于限制性光刻公差的情况下产生小的器件区域的工艺来制造集成器件。该方法使用四个多晶硅层来制造和接触器件区域，以实现相对平面的结构，并且将器件区域的尺寸减小到低于正常光刻公差的尺寸。该过程使用主掩模来定义设备的基本占位面积，并与每个光刻步骤中易于对准的封锁掩模相结合。还描述了可以同时制造的诸如互补横向和垂直双极晶体管，JFET，SIT，MOSFET，电阻器，二极管，电容器和其它器件的许多类型器件的手段和方法。

3. 发明授权

US4837176A Integrated circuit structures having polycrystalline electrode contacts and process 失效
标题翻译：具有多晶电极触点和工艺的集成电路结构
公开(公告)号：US4837176A
公开(公告)日：1989-06-06
申请号：US009322
申请日：1987-01-30
申请人： Peter J. Zdebel , Raymond J. Balda , Bor-Yuan Hwang , Allen J. Wagner
发明人： Peter J. Zdebel , Raymond J. Balda , Bor-Yuan Hwang , Allen J. Wagner
IPC分类号： H01L29/43 , H01L21/033 , H01L21/225 , H01L21/28 , H01L21/285 , H01L21/331 , H01L21/336 , H01L21/337 , H01L21/822 , H01L21/8222 , H01L27/04 , H01L27/06 , H01L29/08 , H01L29/73 , H01L29/732 , H01L29/78 , H01L29/808 , H01L29/861
CPC分类号： H01L21/28525 , H01L21/033 , H01L21/2257
摘要： A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

4. 发明授权

US4806796A Active load for emitter coupled logic gate 失效
标题翻译：发射极耦合逻辑门的有功负载
公开(公告)号：US4806796A
公开(公告)日：1989-02-21
申请号：US174269
申请日：1988-03-28
申请人： Thomas P. Bushey , Bor-Yuan Hwang
发明人： Thomas P. Bushey , Bor-Yuan Hwang
IPC分类号： H03K19/013 , H03K19/086
CPC分类号： H03K19/013 , H03K19/086
摘要： An active load for a CML or ECL logic gate for substantially increasing the speed of the gate comprises a transistor having its base coupled to its collector by a first resistor, and its collector-emitter path coupled in series with a second resistor. This load provides an inductive impedance when the small signal emitter resistance is less than the sum of the resistance of the base and the first resistor, causing a peaking effect resulting in high switching speed.
摘要翻译：用于实质上增加栅极速度的CML或ECL逻辑门的有源负载包括晶体管，其基极通过第一电阻耦合到其集电极，并且其集电极 - 发射极路径与第二电阻器串联耦合。当小信号发射极电阻小于基极和第一电阻器的电阻之和时，此负载提供电感阻抗，导致峰值效应导致高开关速度。

5. 发明授权

US5117391A Bipolar memory cell array biasing technique with forward active PNP load cell 失效
标题翻译：双向存储单元阵列偏置技术与正向有源PNP称重传感器
公开(公告)号：US5117391A
公开(公告)日：1992-05-26
申请号：US533220
申请日：1990-06-04
申请人： Bor-Yuan Hwang , Thomas P. Bushey
发明人： Bor-Yuan Hwang , Thomas P. Bushey
IPC分类号： G11C11/411 , G11C11/415
CPC分类号： G11C11/4113 , G11C11/415
摘要： A bipolar memory array arranged in a row and column matrix is responsive to a plurality of word line driver transistors for selecting one row of memory cells thereof. The current flowing through each memory cell is provided by a pair or lateral PNP transistor current source loads. The collectors of the word line driver transistors are commonly connected for distributing the source of collector current flowing therethrough between the bases of all of the laterla PNP transistor current sources of the entire memory array which maintains a constant current flow through each of the memory cells during the select and deselect cycles thereby maintaining a constant memory cell array power dissipation which allows for expanded capacity of the memory array and a performance improvement.
摘要翻译：布置成行和列矩阵的双极存储器阵列响应于用于选择其一行存储器单元的多个字线驱动器晶体管。流过每个存储单元的电流由一对或横向PNP晶体管电流源负载提供。字线驱动器晶体管的集电极通常被连接用于在整个存储器阵列的所有后置PNP晶体管电流源的基极之间分配流过其的集电极电流源，其保持恒定的电流流过每个存储器单元选择和取消选择周期，从而保持恒定的存储单元阵列功率耗散，这允许存储器阵列的扩展容量和性能改进。

6. 发明授权

US5164326A Complementary bipolar and CMOS on SOI 失效
标题翻译： SOI上的互补双极和CMOS
公开(公告)号：US5164326A
公开(公告)日：1992-11-17
申请号：US860794
申请日：1992-03-30
申请人： Juergen A. Foerstner , Bor-Yuan Hwang , John E. Schmiesing
发明人： Juergen A. Foerstner , Bor-Yuan Hwang , John E. Schmiesing
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/12
CPC分类号： H01L29/66265 , H01L21/8222 , H01L21/8238 , H01L21/8249 , H01L27/0623 , H01L27/1203 , Y10S148/15
摘要： A method for fabricating BiCMOS on SOI. An SOI wafer (14) with an oxide layer (17) and a nitride layer (16) has areas isolated by a LOCOS or mesa isolation (13). A region (15) is defined for CMOS structures from which the insulating layers (17,16) are removed. A gate oxide (21), a polycrystalline silicon layer (22), and a second insulating layer (23,24) is formed. A region for emitters (26) is defined and nitride deposited to form a spacer (27). An oxide layer (28) is grown over the polycrystalline silicon (22) within the emitter region (26). The wafer (14) is etched to the underlying monocrystalline silicon (18) forming base contacts (31). A polycrystalline silicon spacer (36) is formed from a second polycrystalline layer (43) and an oxide spacer (40) is deposited. A region for bipolar collectors (32) and CMOS areas (34) is defined and a spacer (38) deposited.
摘要翻译：在SOI上制造BiCMOS的方法。具有氧化物层（17）和氮化物层（16）的SOI晶片（14）具有通过LOCOS或台面隔离隔离的区域（13）。对于从其去除绝缘层（17,16）的CMOS结构定义区域（15）。形成栅极氧化物（21），多晶硅层（22）和第二绝缘层（23,24）。限定用于发射器（26）的区域，并且氮化物沉积以形成间隔物（27）。在发射极区域（26）内的多晶硅（22）上生长氧化物层（28）。将晶片（14）蚀刻到形成基底触点（31）的下面的单晶硅（18）。多晶硅间隔物（36）由第二多晶层（43）形成，并且沉积氧化物间隔物（40）。限定了用于双极捕获器（32）和CMOS区域（34）的区域并且沉积了间隔物（38）。

7. 发明授权

US4926231A Integrated pin photo-detector 失效
标题翻译：集成引脚光电检测器
公开(公告)号：US4926231A
公开(公告)日：1990-05-15
申请号：US290960
申请日：1988-12-28
申请人： Bor-Yuan Hwang , Carroll M. Casteel , Sal T. Mastroianni
发明人： Bor-Yuan Hwang , Carroll M. Casteel , Sal T. Mastroianni
IPC分类号： H01L27/144
CPC分类号： H01L27/1443
摘要： An improved means and method for forming an optical sensor within an integrated circuit structure is described. An epi-coated semiconductor wafer is masked and a cavity etched through the epi-layer to the underlying substrate. A dielectric sidewall is formed on the cavity sidewall and a substantially intrinsic semiconductor region, preferably grown by selective epitaxy, to refill the cavity. The upper surface of the intrinsic region is then heavily doped and contacted by a low resistance polysilicon layer which is substantially transparent to incoming light. The method forms a high sensitivity PIN photo-sensor having a thick space-charge region for efficient capture of the hole-electron pairs produced by the incoming light. The fabrication techniques are compatible with the processing requirements for other integrated circuit devices formed on the same chip and to which the PIN device is coupled without wire bonds, tabs, bumps or the like.
摘要翻译：描述了用于在集成电路结构内形成光学传感器的改进方法和方法。被外延涂覆的半导体晶片被掩蔽，并且通过外延层蚀刻到下面的衬底上的空腔。电介质侧壁形成在空腔侧壁和基本上本征的半导体区域，优选地通过选择性外延生长以再填充空腔。然后，本征区域的上表面被重掺杂并且被对入射光基本透明的低电阻多晶硅层接触。该方法形成具有厚空间电荷区域的高灵敏度PIN光电传感器，用于有效捕获由入射光产生的空穴 - 电子对。制造技术与形成在同一芯片上的其它集成电路器件的处理要求兼容，并且PIN器件耦合到该器件上而不引线键合，突片等。

8. 发明授权

US5273915A Method for fabricating bipolar junction and MOS transistors on SOI 失效
标题翻译：在SOI上制造双极结和MOS晶体管的方法
公开(公告)号：US5273915A
公开(公告)日：1993-12-28
申请号：US956224
申请日：1992-10-05
申请人： Bor-Yuan Hwang , Juergen A. Foerstner
发明人： Bor-Yuan Hwang , Juergen A. Foerstner
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/12 , H01L29/73 , H01L29/78 , H01L29/786 , H01L21/265
CPC分类号： H01L29/7317 , H01L21/8249 , H01L29/78654 , Y10S148/009 , Y10S148/15
摘要： An SOI wafer (10) is separated into a bipolar junction transistor area (18) and an MOS transistor area (19). A bipolar junction transistor having a collector region (25), and emitter region (44), an inactive base region (33), and an active base region (43) is formed on a thin film of semiconductor material (13) in the bipolar junction transistor area (18). A link between the inactive base region (33) and the active base region (43) is formed from a polysilicon spacer (42) along an edge or sidewall of emitter openings (39 or 40). Simultaneously with the formation of the bipolar junction transistor, MOS transistors are formed in the MOS transistor area (19). Electrically conductive contacts (56) in the bipolar junction transistor area (18) and the MOS transistor area (19) are formed from a silicide. Both complementary bipolar junction transistors and MOS transistors may be formed.

9. 发明授权

US5023479A Low power output gate 失效
标题翻译：低功率输出门
公开(公告)号：US5023479A
公开(公告)日：1991-06-11
申请号：US560920
申请日：1990-07-31
申请人： Philip A. Jeffery , Bor-Yuan Hwang
发明人： Philip A. Jeffery , Bor-Yuan Hwang
IPC分类号： H03K19/08 , H03K19/00 , H03K19/086 , H03K19/0944
CPC分类号： H03K19/001 , H03K19/09448
摘要： A low power BiMOS output gate includes an input circuit for passing current through its first and second outputs in response to logic states occurring on first and second input signals which are respectively applied at first and second inputs of the input circuit. A field-effect transistor has first and second electrodes and a control electrode, the control electrode is coupled to the first output of the input circuit, the first electrode is coupled to the second output of the input circuit, and the second electrode is coupled to a first supply voltage terminal. A first resistor is coupled across the second and control electrodes of the field-effect transistor while a second resistor is coupled across the first and second electrodes of the field-effect transistor such that when the first input signal is in a first logic state, the voltage drop occurring across the first resistor will render the field-effect transistor operative wherein the effective resistance of the second resistor is decreased. Also, an output circuit is coupled to the second output of the input circuit for providing an output logic signal at an output terminal of the BiMOS output gate.
摘要翻译：低功率BiMOS输出门包括输入电路，用于响应于分别在输入电路的第一和第二输入端施加的第一和第二输入信号上发生的逻辑状态而使电流通过其第一和第二输出。场效应晶体管具有第一和第二电极和控制电极，控制电极耦合到输入电路的第一输出，第一电极耦合到输入电路的第二输出，第二电极耦合到第一电源电压端子。第一电阻器耦合在场效应晶体管的第二和控制电极之间，而第二电阻器耦合在场效应晶体管的第一和第二电极两端，使得当第一输入信号处于第一逻辑状态时，在第一电阻器两端发生的电压降将导致场效应晶体管工作，其中第二电阻器的有效电阻降低。此外，输出电路耦合到输入电路的第二输出端，用于在BiMOS输出门的输出端提供输出逻辑信号。

10. 发明授权

US4847210A Integrated pin photo-detector method 失效
标题翻译：集成针式光电探测器方法
公开(公告)号：US4847210A
公开(公告)日：1989-07-11
申请号：US228646
申请日：1988-08-05
申请人： Bor-Yuan Hwang , Carroll M. Casteel , Sal T. Mastroianni
发明人： Bor-Yuan Hwang , Carroll M. Casteel , Sal T. Mastroianni
IPC分类号： H01L31/10 , H01L27/14 , H01L27/144
CPC分类号： H01L27/1443
摘要： An improved means and method for forming an optical sensor within an integrated circuit structure is described. An epi-coated semiconductor wafer is masked and a cavity etched through the epi-layer to the underlying substrate. A dielectric sidewall is formed on the cavity sidewall and a substantially intrinsic semiconductor region, preferably grown by selective epitaxy, to refill the cavity. The upper surface of the intrinsic region is then heavily doped and contacted by a low resistance polysilicon layer which is substantially transparent to incoming light. The method forms a high sensitivity PIN photo-sensor having a thick space-charge region for efficient capture of the hole-electron pairs produced by the incoming light. The fabrication techniques are compatible with the processing requirements for other integrated circuit devices formed on the same chip and to which the PIN device is coupled without wire bonds, tabs, bumps or the like.
摘要翻译：描述了用于在集成电路结构内形成光学传感器的改进方法和方法。被外延涂覆的半导体晶片被掩蔽，并且通过外延层蚀刻到下面的衬底上的空腔。电介质侧壁形成在空腔侧壁和基本上本征的半导体区域，优选地通过选择性外延生长以再填充空腔。然后，本征区域的上表面被重掺杂并且被对入射光基本透明的低电阻多晶硅层接触。该方法形成具有厚空间电荷区域的高灵敏度PIN光电传感器，用于有效捕获由入射光产生的空穴 - 电子对。制造技术与形成在同一芯片上的其它集成电路器件的处理要求兼容，并且PIN器件耦合到该器件上而不引线键合，突片等。

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