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1. 发明授权

US07528062B2 Integrated matching network and method for manufacturing integrated matching networks 有权
标题翻译：综合匹配网络和制造综合匹配网络的方法
公开(公告)号：US07528062B2
公开(公告)日：2009-05-05
申请号：US11586807
申请日：2006-10-25
申请人： Melvy F. Miller , Juergen A. Foerstner
发明人： Melvy F. Miller , Juergen A. Foerstner
IPC分类号： H01L21/44 , H01L23/52
CPC分类号： H01L23/66 , H01L25/0655 , H01L2223/6655 , H01L2224/16227 , H01L2224/16235 , H01L2224/32245 , H01L2224/73253 , H01L2924/0002 , H01L2924/15192 , H01L2924/19104 , H01L2924/3011 , H01L2924/00
摘要： An integrated matching network and method for manufacturing an integrated matching network are provided. The method includes forming (405) a first die on a substrate, forming (410) a second die on the substrate, and forming (415) a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a PA (101), a second die having a capacitor (102), and a metal interconnect (108) coupled to the PA and the first capacitor. The metal interconnect (108) has an inductance. The capacitor (102) and metal interconnect (108) form a shunt impedance.
摘要翻译：提供了一种用于制造集成匹配网络的集成匹配网络和方法。该方法包括在衬底上形成（405）第一管芯，在衬底上形成（410）第二管芯，以及在第一和第二管芯上形成（415）金属化层。第二管芯具有电容，金属化层具有电感，并且电容和电感一起提供从第一管芯到衬底的分流阻抗。集成匹配网络包括具有PA（101）的第一管芯，具有电容器（102）的第二管芯和耦合到PA和第一电容器的金属互连（108）。金属互连（108）具有电感。电容器（102）和金属互连（108）形成分流阻抗。

2. 发明授权

US06770569B2 Low temperature plasma Si or SiGe for MEMS applications 有权
标题翻译：用于MEMS应用的低温等离子体Si或SiGe
公开(公告)号：US06770569B2
公开(公告)日：2004-08-03
申请号：US10210315
申请日：2002-08-01
申请人： Juergen A. Foerstner , Steven M. Smith , Raymond Mervin Roop
发明人： Juergen A. Foerstner , Steven M. Smith , Raymond Mervin Roop
IPC分类号： H01L2131
CPC分类号： B81C1/0038 , B81B2201/018 , B81B2201/0292 , B81C1/00246 , B81C2201/0164 , B81C2203/0735 , H01G5/18
摘要： A method is provided for making a MEMS structure (69). In accordance with the method, a CMOS substrate (51) is provided which has interconnect metal (53) deposited thereon. A MEMS structure is created on the substrate through the plasma assisted chemical vapor deposition (PACVD) of a material selected from the group consisting of silicon and silicon-germanium alloys. The low deposition temperatures attendant to the use of PACVD allow these materials to be used for MEMS fabrication at the back end of an integrated CMOS process.
摘要翻译：提供了一种用于制造MEMS结构（69）的方法。根据该方法，提供具有沉积在其上的互连金属（53）的CMOS基板（51）。通过等离子体辅助化学气相沉积（PACVD）在由硅和硅 - 锗合金组成的组中选择的材料在衬底上产生MEMS结构。使用PACVD的低沉积温度允许这些材料用于集成CMOS工艺后端的MEMS制造。

3. 发明授权

US5792678A Method for fabricating a semiconductor on insulator device 失效
标题翻译：半导体绝缘体器件的制造方法
公开(公告)号：US5792678A
公开(公告)日：1998-08-11
申请号：US642134
申请日：1996-05-02
申请人： Juergen A. Foerstner , Wen-Ling M. Huang , Marco Racanelli
发明人： Juergen A. Foerstner , Wen-Ling M. Huang , Marco Racanelli
IPC分类号： H01L21/84 , H01L27/12 , H01L21/8249
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor on insulator structure (50) includes a silicon layer (30) formed on an insulating substrate (20). The silicon layer (30) is partitioned into two sections (32, 34) which are electrically isolated from each other. The thickness of the silicon layer (30) in a first section (32) of the silicon layer (30) is adjusted independently from the thickness of the silicon layer (30) in a second section (34) of the silicon layer (30). Independently adjusting the thickness of the silicon layer (30) allows optimizing the performance of semiconductor devices (60, 80) fabricated in the first and second sections (32, 34) of the semiconductor on insulator structure (50).
摘要翻译：半导体绝缘体结构（50）包括形成在绝缘基板（20）上的硅层（30）。硅层（30）被分隔成彼此电绝缘的两个部分（32,34）。在硅层（30）的第二部分（34）中，与硅层（30）的厚度独立地调节硅层（30）的第一部分（32）中的硅层（30）的厚度，。独立地调整硅层（30）的厚度允许优化在半导体绝缘体结构（50）的第一和第二部分（32,34）中制造的半导体器件（60,80）的性能。

4. 发明授权

US5164326A Complementary bipolar and CMOS on SOI 失效
标题翻译： SOI上的互补双极和CMOS
公开(公告)号：US5164326A
公开(公告)日：1992-11-17
申请号：US860794
申请日：1992-03-30
申请人： Juergen A. Foerstner , Bor-Yuan Hwang , John E. Schmiesing
发明人： Juergen A. Foerstner , Bor-Yuan Hwang , John E. Schmiesing
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/12
CPC分类号： H01L29/66265 , H01L21/8222 , H01L21/8238 , H01L21/8249 , H01L27/0623 , H01L27/1203 , Y10S148/15
摘要： A method for fabricating BiCMOS on SOI. An SOI wafer (14) with an oxide layer (17) and a nitride layer (16) has areas isolated by a LOCOS or mesa isolation (13). A region (15) is defined for CMOS structures from which the insulating layers (17,16) are removed. A gate oxide (21), a polycrystalline silicon layer (22), and a second insulating layer (23,24) is formed. A region for emitters (26) is defined and nitride deposited to form a spacer (27). An oxide layer (28) is grown over the polycrystalline silicon (22) within the emitter region (26). The wafer (14) is etched to the underlying monocrystalline silicon (18) forming base contacts (31). A polycrystalline silicon spacer (36) is formed from a second polycrystalline layer (43) and an oxide spacer (40) is deposited. A region for bipolar collectors (32) and CMOS areas (34) is defined and a spacer (38) deposited.
摘要翻译：在SOI上制造BiCMOS的方法。具有氧化物层（17）和氮化物层（16）的SOI晶片（14）具有通过LOCOS或台面隔离隔离的区域（13）。对于从其去除绝缘层（17,16）的CMOS结构定义区域（15）。形成栅极氧化物（21），多晶硅层（22）和第二绝缘层（23,24）。限定用于发射器（26）的区域，并且氮化物沉积以形成间隔物（27）。在发射极区域（26）内的多晶硅（22）上生长氧化物层（28）。将晶片（14）蚀刻到形成基底触点（31）的下面的单晶硅（18）。多晶硅间隔物（36）由第二多晶层（43）形成，并且沉积氧化物间隔物（40）。限定了用于双极捕获器（32）和CMOS区域（34）的区域并且沉积了间隔物（38）。

5. 发明申请

US20080099800A1 Integrated matching network and method for manufacturing integrated matching networks 有权
标题翻译：综合匹配网络和制造综合匹配网络的方法
公开(公告)号：US20080099800A1
公开(公告)日：2008-05-01
申请号：US11586807
申请日：2006-10-25
申请人： Melvy F. Miller , Juergen A. Foerstner
发明人： Melvy F. Miller , Juergen A. Foerstner
IPC分类号： H01L29/80 , H01L23/48
CPC分类号： H01L23/66 , H01L25/0655 , H01L2223/6655 , H01L2224/16227 , H01L2224/16235 , H01L2224/32245 , H01L2224/73253 , H01L2924/0002 , H01L2924/15192 , H01L2924/19104 , H01L2924/3011 , H01L2924/00
摘要： An integrated matching network and method for manufacturing an integrated matching network are provided. The method includes forming (405) a first die on a substrate, forming (410) a second die on the substrate, and forming (415) a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a PA (101), a second die having a capacitor (102), and a metal interconnect (108) coupled to the PA and the first capacitor. The metal interconnect (108) has an inductance. The capacitor (102) and metal interconnect (108) form a shunt impedance.
摘要翻译：提供了一种用于制造集成匹配网络的集成匹配网络和方法。该方法包括在衬底上形成（405）第一管芯，在衬底上形成（410）第二管芯，以及在第一和第二管芯上形成（415）金属化层。第二管芯具有电容，金属化层具有电感，并且电容和电感一起提供从第一管芯到衬底的分流阻抗。集成匹配网络包括具有PA（101）的第一管芯，具有电容器（102）的第二管芯和耦合到PA和第一电容器的金属互连（108）。金属互连（108）具有电感。电容器（102）和金属互连（108）形成分流阻抗。

6. 发明授权

US6105428A Sensor and method of use 失效
标题翻译：传感器和使用方法
公开(公告)号：US6105428A
公开(公告)日：2000-08-22
申请号：US209116
申请日：1998-12-10
申请人： John E. Schmiesing , Guang X. Li , Juergen A. Foerstner , Muh-Ling Ger , Paul L. Bergstrom , Frank A. Shemansky, Jr.
发明人： John E. Schmiesing , Guang X. Li , Juergen A. Foerstner , Muh-Ling Ger , Paul L. Bergstrom , Frank A. Shemansky, Jr.
IPC分类号： G01P15/08 , G01P15/125
CPC分类号： G01P15/125 , G01P15/0802 , G01P2015/0814
摘要： A sensor has an electrode (120) that is movable along three mutually perpendicular axes (10, 11, 12). The sensor also has stationary over-travel limiting structures that restrict the movement of the electrode (120) along the three axes (10, 11, 12).
摘要翻译：传感器具有可沿三个相互垂直的轴线（10,11,12）移动的电极（120）。传感器还具有限制电极（120）沿着三个轴线（10,11,12）的运动的静止的超行程限制结构。

7. 发明授权

US5719081A Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant 失效
标题翻译：使用两级阈值调整植入物在绝缘体上半导体衬底上的半导体器件的制造方法
公开(公告)号：US5719081A
公开(公告)日：1998-02-17
申请号：US552656
申请日：1995-11-03
申请人： Marco Racanelli , Wen-Ling M. Huang , Bor-Yuan C. Hwang , Juergen A. Foerstner
发明人： Marco Racanelli , Wen-Ling M. Huang , Bor-Yuan C. Hwang , Juergen A. Foerstner
IPC分类号： H01L21/336 , H01L29/10 , H01L29/786
CPC分类号： H01L29/78696 , H01L29/105 , H01L29/66772 , H01L29/78609 , H01L29/78621
摘要： A two stage threshold adjust implantation process is performed after field oxidation to avoid the effects of dopant redistribution and segregation. At any of several steps in a manufacturing process, only routine implant energy and dose adjustments are required to create a first and a second dopant profile (110, 120) that result in the reduction of edge leakage and threshold voltage sensitivity to device layer thickness of a semiconductor device on a semiconductor on insulator substrate.
摘要翻译：在场氧化后进行两级阈值调整注入工艺，以避免掺杂剂再分布和分离的影响。在制造过程中的几个步骤中的任何一个步骤中，仅需要常规的植入能量和剂量调整以产生第一和第二掺杂剂分布（110,120），其导致边缘泄漏的减小和对器件层厚度的阈值电压敏感性半导体衬底上的半导体器件。

8. 发明授权

US07667334B2 Integrated matching networks and RF devices that include an integrated matching network 有权
标题翻译：集成匹配网络和RF设备，包括集成匹配网络
公开(公告)号：US07667334B2
公开(公告)日：2010-02-23
申请号：US12390549
申请日：2009-02-23
申请人： Melvy F. Miller , Juergen A. Foerstner
发明人： Melvy F. Miller , Juergen A. Foerstner
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L23/66 , H01L25/0655 , H01L2223/6655 , H01L2224/16227 , H01L2224/16235 , H01L2224/32245 , H01L2224/73253 , H01L2924/0002 , H01L2924/15192 , H01L2924/19104 , H01L2924/3011 , H01L2924/00
摘要： An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a power amplifier, a second die having a capacitor, and a metal interconnect coupled to the power amplifier and the first capacitor. The metal interconnect has an inductance. The capacitor and metal interconnect form a shunt impedance.
摘要翻译：集成匹配网络包括衬底上的第一裸片，衬底上的第二裸片，以及第一和第二裸片上的金属化层。第二管芯具有电容，金属化层具有电感，并且电容和电感一起提供从第一管芯到衬底的分流阻抗。集成匹配网络包括具有功率放大器的第一管芯，具有电容器的第二管芯和耦合到功率放大器和第一电容器的金属互连。金属互连具有电感。电容器和金属互连形成分流阻抗。

9. 发明申请

US20090152698A1 INTEGRATED MATCHING NETWORKS AND RF DEVICES THAT INCLUDE AN INTEGRATED MATCHING NETWORK 有权
标题翻译：集成匹配网络和包含一体化匹配网络的射频设备
公开(公告)号：US20090152698A1
公开(公告)日：2009-06-18
申请号：US12390549
申请日：2009-02-23
申请人： Melvy F. Miller , Juergen A. Foerstner
发明人： Melvy F. Miller , Juergen A. Foerstner
IPC分类号： H01L23/00
CPC分类号： H01L23/66 , H01L25/0655 , H01L2223/6655 , H01L2224/16227 , H01L2224/16235 , H01L2224/32245 , H01L2224/73253 , H01L2924/0002 , H01L2924/15192 , H01L2924/19104 , H01L2924/3011 , H01L2924/00
摘要： An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a power amplifier, a second die having a capacitor, and a metal interconnect coupled to the power amplifier and the first capacitor. The metal interconnect has an inductance. The capacitor and metal interconnect form a shunt impedance.
摘要翻译：集成匹配网络包括衬底上的第一裸片，衬底上的第二裸片，以及第一和第二裸片上的金属化层。第二管芯具有电容，金属化层具有电感，并且电容和电感一起提供从第一管芯到衬底的分流阻抗。集成匹配网络包括具有功率放大器的第一管芯，具有电容器的第二管芯和耦合到功率放大器和第一电容器的金属互连。金属互连具有电感。电容器和金属互连形成分流阻抗。

10. 发明授权

US07226802B2 Tungsten coated silicon fingers 有权
标题翻译：镀钨硅指
公开(公告)号：US07226802B2
公开(公告)日：2007-06-05
申请号：US10914006
申请日：2004-08-06
申请人： Paul M. Ocansey , Juergen A. Foerstner
发明人： Paul M. Ocansey , Juergen A. Foerstner
IPC分类号： H01L21/00
CPC分类号： B81B3/0005 , B81B2201/0235 , B81C1/0096 , B81C2201/112 , C23C16/14 , G01P15/0802 , G01P15/125
摘要： Methods and apparatus are provided for preparing sensing fingers for use in a highly integrated accelerometer. The method includes steps for forming a tungsten/tungsten silicide coating on a silicon finger. The tungsten/tungsten silicide coating adds mass to the silicon finger. The method includes steps of forming silicon fingers from layers of silicon, oxides, and capping material. The silicon fingers are then exposed to tungsten containing gases under conditions to promote the formation of a tungsten silicide seed layer on the exposed silicon surfaces. The tungsten layer is then grown to a desired thickness through a growth step. The coated silicon fingers display improved resistance to stiction as compared to uncoated silicon fingers.
摘要翻译：提供了用于准备用于高度集成的加速度计中的传感指的方法和装置。该方法包括在硅指状物上形成钨/硅化钨涂层的步骤。钨/硅化钨涂层增加了硅胶的质量。该方法包括从硅，氧化物和封盖材料层形成硅指的步骤。然后在允许在暴露的硅表面上形成硅化钨晶种层的条件下将硅指暴露于含钨气体的条件下。然后通过生长步骤将钨层生长至所需厚度。与未涂覆的硅指相比，涂覆的硅指显示改进的粘性阻力。

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