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1. 发明授权

US06995376B2 Silicon-on-insulator latch-up pulse-radiation detector 有权
标题翻译：绝缘体上电锁存脉冲辐射检测器
公开(公告)号：US06995376B2
公开(公告)日：2006-02-07
申请号：US10604204
申请日：2003-07-01
申请人： Peter E. Cottrell , Robert H. Dennard , Edward J. Nowak , Norman J. Rohrer
发明人： Peter E. Cottrell , Robert H. Dennard , Edward J. Nowak , Norman J. Rohrer
IPC分类号： G01T1/24
CPC分类号： H01L31/1113
摘要： A radiation detector formed using silicon-on-insulator technology. The radiation detector includes a silicon layer formed on an insulating substrate, wherein the silicon layer includes a PNPN structure, and a gate layer formed over the PNPN structure, wherein the gate layer includes a PN gate. Latch-up occurs in the radiation detector only in response to incident radiation.
摘要翻译：使用绝缘体上硅技术形成的放射线检测器。放射线检测器包括形成在绝缘基板上的硅层，其中硅层包括PNPN结构，以及形成在PNPN结构上的栅极层，其中栅极层包括PN栅极。仅在响应入射辐射的情况下，在辐射探测器中发生锁定。

2. 发明授权

US06580293B1 Body-contacted and double gate-contacted differential logic circuit and method of operation 有权
标题翻译：身体接触和双门接触差分逻辑电路及其操作方法
公开(公告)号：US06580293B1
公开(公告)日：2003-06-17
申请号：US09683325
申请日：2001-12-14
申请人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
发明人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
IPC分类号： H03K19096
CPC分类号： H03K19/1737 , H03K3/356113 , H03K19/0963
摘要： A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.
摘要翻译：设计用于确保电路输出的稳定性的差分逻辑电路（20,120,220,320,420和520）。逻辑电路包括被连接以评估晶体管（50,52,54,56）的差分负载结构（22,122,222,322,422）。在几个实施例中，差分负载结构中的负载晶体管（30,32）的输出连接到评估晶体管的主体。在其他实施例中，差分结构中的负载晶体管的输出连接到双门控评估晶体管的栅极之一。结合本发明的不包括双门控评估晶体管的实施例，使用电平移位输出缓冲器（160,178）。

3. 发明授权

US06577178B1 Transient gate tunneling current control 有权
标题翻译：瞬态栅极隧道电流控制
公开(公告)号：US06577178B1
公开(公告)日：2003-06-10
申请号：US10064504
申请日：2002-07-23
申请人： Kerry Bernstein , Peter E. Cottrell , Edward J. Nowak , Norman J. Rohrer , Douglas W. Stout
发明人： Kerry Bernstein , Peter E. Cottrell , Edward J. Nowak , Norman J. Rohrer , Douglas W. Stout
IPC分类号： H03K1730
CPC分类号： H03K19/00361 , H03K19/0948
摘要： A circuit includes a resistance-capacitance (RC) structure connected to a first set of transistors and a second set of transistors that perform the same logical function as the first set of transistors. The first set of transistors have thinner gate oxides than the second set of transistors. The RC structure drains an electric field from the first set of transistors, such that the first set of transistors are on only during initial transistor switching. In other words, the RC structure turns off the first set of transistors after transistor switching is completed. Also, the first set of transistors and the second set of transistors share common inputs and outputs. The first set of transistors exhibit higher tunneling currents than the second set of transistors. The thinner gate oxides of the first set of transistors cause the first set of transistors to exhibit higher device currents than the second set of transistors. The RC structure includes a capacitor connected to a gate of the first set of transistors and a resistor connected to the capacitor and to ground.
摘要翻译：电路包括连接到第一组晶体管的电阻 - 电容（RC）结构和执行与第一组晶体管相同的逻辑功能的第二组晶体管。第一组晶体管具有比第二组晶体管更薄的栅极氧化物。 RC结构从第一组晶体管引出电场，使得第一组晶体管仅在初始晶体管切换期间导通。换句话说，在晶体管切换完成之后，RC结构关闭第一组晶体管。此外，第一组晶体管和第二组晶体管共享公共输入和输出。第一组晶体管表现出比第二组晶体管更高的隧穿电流。第一组晶体管的较薄的栅极氧化物导致第一组晶体管表现出比第二组晶体管更高的器件电流。 RC结构包括连接到第一组晶体管的栅极的电容器和连接到电容器并接地的电阻器。

4. 发明授权

US07075153B2 Grounded body SOI SRAM cell 有权
标题翻译：接地体SOI SRAM单元
公开(公告)号：US07075153B2
公开(公告)日：2006-07-11
申请号：US10640807
申请日：2003-08-14
申请人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
发明人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L27/1203 , H01L27/1104
摘要： A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.
摘要翻译：一种半导体存储器件，包括：在衬底绝缘体的顶部上具有薄硅层的SOI衬底; 以及包括四个NFET和位于薄硅层中的两个PFET的SRAM，每个NFET和PFET具有在源极区域和漏极区域之间的主体区域，其中两个NFET的主体电连接到地。另外，两个PFET的主体电连接到V DD。

5. 发明授权

US06646305B2 Grounded body SOI SRAM cell 有权
标题翻译：接地体SOI SRAM单元
公开(公告)号：US06646305B2
公开(公告)日：2003-11-11
申请号：US09915061
申请日：2001-07-25
申请人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
发明人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L27/1104
摘要： A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.
摘要翻译：一种半导体存储器件，包括：在衬底绝缘体的顶部上具有薄硅层的SOI衬底; 以及包括四个NFET和位于薄硅层中的两个PFET的SRAM，每个NFET和PFET具有在源极区域和漏极区域之间的主体区域，其中两个NFET的主体电连接到地。另外，两个PFET的主体电连接到VDD。

6. 发明授权

US06940130B2 Body contact MOSFET 失效
标题翻译：体接触MOSFET
公开(公告)号：US06940130B2
公开(公告)日：2005-09-06
申请号：US10687333
申请日：2003-10-16
申请人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
发明人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
IPC分类号： H01L21/336 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.
摘要翻译：公开了一种在有源区的主体接触部分和有源区的晶体管部分之间利用绝缘结构的体接触结构。在一个实施例中，本发明将绝缘体替代晶体管和身体接触之间的区域中的栅极层的至少一部分。在另一个实施例中，栅极层的一部分被去除并且在晶体管和身体接触之间的区域中被绝缘层替代。在另一个实施例中，通过在晶体管和身体接触之间的区域中在栅极和主体之间形成多个栅极电介质层来形成绝缘结构。通过这些方法产生的身体接触对栅极没有增加显着的栅极电容。

7. 发明授权

US06677645B2 Body contact MOSFET 有权
标题翻译：体接触MOSFET
公开(公告)号：US06677645B2
公开(公告)日：2004-01-13
申请号：US10061263
申请日：2002-01-31
申请人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
发明人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.
摘要翻译：公开了一种在有源区的主体接触部分和有源区的晶体管部分之间利用绝缘结构的体接触结构。在一个实施例中，本发明将绝缘体替代晶体管和身体接触之间的区域中的栅极层的至少一部分。在另一个实施例中，栅极层的一部分被去除并且在晶体管和身体接触之间的区域中被绝缘层替代。在另一个实施例中，通过在晶体管和身体接触之间的区域中在栅极和主体之间形成多个栅极电介质层来形成绝缘结构。通过这些方法产生的身体接触对栅极没有增加显着的栅极电容。

8. 发明授权

US4470191A Process for making complementary transistors by sequential implantations using oxidation barrier masking layer 失效
标题翻译：通过使用氧化屏障掩蔽层的顺序注入来制造互补晶体管的工艺
公开(公告)号：US4470191A
公开(公告)日：1984-09-11
申请号：US448125
申请日：1982-12-09
申请人： Peter E. Cottrell , Henry J. Geipel, Jr. , Donald M. Kenney
发明人： Peter E. Cottrell , Henry J. Geipel, Jr. , Donald M. Kenney
IPC分类号： H01L27/08 , H01L21/762 , H01L21/8238 , H01L29/78 , H01L7/54 , B01J17/00 , H01L21/265
CPC分类号： H01L21/823878 , H01L21/76218 , Y10S438/975
摘要： A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.
摘要翻译：提供了一种制造平面CMOS结构的简单方法，其中首先形成体CMOS结构所需的隔离区域，N沟道器件场区域与半导体衬底中的N阱区域自对准，并且耐火材料被两次限定形成P和N通道，第一定义屏蔽P沟道源极和漏极区域，同时定义N沟道，并且第二定义限定P沟道，同时使用光致抗蚀剂层掩蔽N沟道。在该过程中，使用单个掩模级别的技术定义了阱区域并将必要的场掺杂自对准到阱区域以提供紧密间隔的N沟道和P沟道器件。

9. 发明授权

US4382229A Channel hot electron monitor 失效
标题翻译：通道热电子监视器
公开(公告)号：US4382229A
公开(公告)日：1983-05-03
申请号：US210937
申请日：1980-11-28
申请人： Peter E. Cottrell , Ronald R. Troutman
发明人： Peter E. Cottrell , Ronald R. Troutman
IPC分类号： G01R31/26 , G01R31/22
CPC分类号： G01R31/2621
摘要： This teaches that by measuring the rate of change in gate current of an insulating gate field effect transistor, under normal operating conditions, the time required to achieve a predetermined change in source-to-drain current in the transistor can be found. Because changes in gate current depends more on sensitivity on charge trapping in the oxide than do changes in channel current, and since the gate current occurs only in the small region of electron emission, the effects on gate current are more quickly developed than the secondary effect of reduced channel current due to the charge in gate oxide caused by the presence of trapped electrons.
摘要翻译：这表明，通过测量绝缘栅场效应晶体管的栅极电流的变化率，在正常工作条件下，可以找到实现晶体管中源极 - 漏极电流的预定变化所需的时间。因为栅极电流的变化更多地取决于在沟道电流中改变氧化物中的电荷捕获的灵敏度，并且由于栅极电流仅发生在电子发射的小区域中，所以对栅极电流的影响比次级效应更快地发展由于俘获电子的存在引起的栅极氧化物中的电荷引起的沟道电流减小。

10. 发明授权

US4480375A Simple process for making complementary transistors 失效
标题翻译：制造互补晶体管的简单过程
公开(公告)号：US4480375A
公开(公告)日：1984-11-06
申请号：US448124
申请日：1982-12-09
申请人： Peter E. Cottrell , Henry J. Geipel, Jr.
发明人： Peter E. Cottrell , Henry J. Geipel, Jr.
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78 , H01L21/22 , H01L21/263
CPC分类号： H01L21/823814 , Y10S438/981
摘要： A very simple process is provided, with reduced processing time, for making a CMOS structure using a single polysilicon, or other refractory metal, layer which includes forming a thin gate oxide on both N and P type semiconductor layers of a common substrate, forming a gate electrode simultaneously on the N type and on the P type layers and selectively implanting an N type impurity to form N+ source and drain regions in the P type layer. The semiconductor layers are then oxidized to form substantially thicker oxide, such a silicon dioxide, adjacent to the sides of the gate electrode over the P type layer than the thickness of the oxide adjacent to the sides of the gate electrode over the N type layer. Without using a mask, a P type impurity is implanted into the N type layer to form P+ source and drain regions.
摘要翻译：提供了一种非常简单的方法，缩短了处理时间，用于制造使用单个多晶硅的CMOS结构或其它难熔金属层，其包括在公共基板的N型和P型半导体层上形成薄的栅极氧化物，形成栅电极同时在N型和P型层上，并且选择性地注入N型杂质以在P型层中形成N +源极和漏极区。然后氧化氧化半导体层以形成比在N型层上与栅电极相邻的氧化物的厚度相邻的，比P型层更靠近栅电极侧面的基本上较厚的氧化物，例如二氧化硅。在不使用掩模的情况下，将P型杂质注入到N型层中以形成P +源极和漏极区。

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