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1. 发明授权

US4470191A Process for making complementary transistors by sequential implantations using oxidation barrier masking layer 失效
标题翻译：通过使用氧化屏障掩蔽层的顺序注入来制造互补晶体管的工艺
公开(公告)号：US4470191A
公开(公告)日：1984-09-11
申请号：US448125
申请日：1982-12-09
申请人： Peter E. Cottrell , Henry J. Geipel, Jr. , Donald M. Kenney
发明人： Peter E. Cottrell , Henry J. Geipel, Jr. , Donald M. Kenney
IPC分类号： H01L27/08 , H01L21/762 , H01L21/8238 , H01L29/78 , H01L7/54 , B01J17/00 , H01L21/265
CPC分类号： H01L21/823878 , H01L21/76218 , Y10S438/975
摘要： A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.
摘要翻译：提供了一种制造平面CMOS结构的简单方法，其中首先形成体CMOS结构所需的隔离区域，N沟道器件场区域与半导体衬底中的N阱区域自对准，并且耐火材料被两次限定形成P和N通道，第一定义屏蔽P沟道源极和漏极区域，同时定义N沟道，并且第二定义限定P沟道，同时使用光致抗蚀剂层掩蔽N沟道。在该过程中，使用单个掩模级别的技术定义了阱区域并将必要的场掺杂自对准到阱区域以提供紧密间隔的N沟道和P沟道器件。

2. 发明授权

US4480375A Simple process for making complementary transistors 失效
标题翻译：制造互补晶体管的简单过程
公开(公告)号：US4480375A
公开(公告)日：1984-11-06
申请号：US448124
申请日：1982-12-09
申请人： Peter E. Cottrell , Henry J. Geipel, Jr.
发明人： Peter E. Cottrell , Henry J. Geipel, Jr.
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78 , H01L21/22 , H01L21/263
CPC分类号： H01L21/823814 , Y10S438/981
摘要： A very simple process is provided, with reduced processing time, for making a CMOS structure using a single polysilicon, or other refractory metal, layer which includes forming a thin gate oxide on both N and P type semiconductor layers of a common substrate, forming a gate electrode simultaneously on the N type and on the P type layers and selectively implanting an N type impurity to form N+ source and drain regions in the P type layer. The semiconductor layers are then oxidized to form substantially thicker oxide, such a silicon dioxide, adjacent to the sides of the gate electrode over the P type layer than the thickness of the oxide adjacent to the sides of the gate electrode over the N type layer. Without using a mask, a P type impurity is implanted into the N type layer to form P+ source and drain regions.
摘要翻译：提供了一种非常简单的方法，缩短了处理时间，用于制造使用单个多晶硅的CMOS结构或其它难熔金属层，其包括在公共基板的N型和P型半导体层上形成薄的栅极氧化物，形成栅电极同时在N型和P型层上，并且选择性地注入N型杂质以在P型层中形成N +源极和漏极区。然后氧化氧化半导体层以形成比在N型层上与栅电极相邻的氧化物的厚度相邻的，比P型层更靠近栅电极侧面的基本上较厚的氧化物，例如二氧化硅。在不使用掩模的情况下，将P型杂质注入到N型层中以形成P +源极和漏极区。

3. 发明授权

US4389257A Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes 失效
标题翻译：高导电性无空隙多晶硅集成电路电极的制造方法
公开(公告)号：US4389257A
公开(公告)日：1983-06-21
申请号：US288608
申请日：1981-07-30
申请人： Henry J. Geipel, Jr. , Ning Hsieh , Charles W. Koburger, III , Larry A. Nesbit
发明人： Henry J. Geipel, Jr. , Ning Hsieh , Charles W. Koburger, III , Larry A. Nesbit
IPC分类号： H01L29/78 , H01L21/28 , H01L21/321 , H01L21/336 , H01L21/768 , H01L29/423 , H01L29/43 , H01L29/49 , H01L21/285
CPC分类号： H01L29/4975 , H01L21/28061 , H01L21/321 , H01L21/76889 , Y10S148/147
摘要： A method of providing self-passivating interconnection electrodes for semiconductor devices which provides low resistivity composite polysiliconsilicide electrodes. In the method the formation of oxidation induced voids in polysilicon underlying the silicide is eliminated by deposition of polysilicon and stoichiometric proportions of silicon and a silicide-forming metal. These steps are followed by deposition of a silicon layer having a thickness determined to provide between 30 and 100 percent of the silicon required to form a silicon dioxide passivation layer. Subsequent thermal oxidation of the layered electrode structure provides a self-passivated structure useful for fabrication of silicon gate MOSFET devices as well as other integrated circuit structures.
摘要翻译：一种提供半导体器件的自钝化互连电极的方法，其提供低电阻率复合多硅化物电极。在该方法中，通过沉积多晶硅和化学计量比例的硅和形成硅化物的金属来消除在硅化物下面的多晶硅中形成氧化诱发的空隙。这些步骤之后是沉积具有确定提供形成二氧化硅钝化层所需的硅的30％至100％的厚度的硅层。层状电极结构的随后的热氧化提供了用于制造硅栅极MOSFET器件以及其它集成电路结构的自钝化结构。

4. 发明授权

US4462151A Method of making high density complementary transistors 失效
标题翻译：制造高密度互补晶体管的方法
公开(公告)号：US4462151A
公开(公告)日：1984-07-31
申请号：US446793
申请日：1982-12-03
申请人： Henry J. Geipel, Jr. , Ronald R. Troutman , John M. Wursthorn
发明人： Henry J. Geipel, Jr. , Ronald R. Troutman , John M. Wursthorn
IPC分类号： H01L27/08 , H01L21/8238 , H01L29/06 , H01L29/49 , H01L29/78 , H01L21/22 , H01L11/14
CPC分类号： H01L29/495 , H01L21/823814 , H01L21/823828 , H01L29/0638 , H01L29/4975
摘要： A simple process is provided which forms a bulk CMOS structure by depositing a layer of material which resists oxidation, e.g., a barrier layer of silicon nitride on an N- semiconductor substrate, forming a P well in the substrate through a given segment of the barrier layer, removing a first segment of the barrier layer to form N+ regions for N channel source and drain and N- substrate contact, removing a second segment of the barrier layer to form a P+ field region, removing a third segment of the barrier layer to form P+ regions for source and drain of a P channel device, forming a first control electrode having a given work function for the P channel device which acts as an ion barrier and then forming a second control electrode between the N channel source and drain regions having a work function different from that of the first control electrode.
摘要翻译：提供了一种简单的方法，其通过沉积抗氧化的材料层（例如，在N-半导体衬底上的氮化硅阻挡层）形成体CMOS结构，通过势垒的给定段在衬底中形成P阱去除阻挡层的第一段以形成用于N沟道源极和漏极和N-衬底接触的N +区域，去除阻挡层的第二部分以形成P +场区域，去除阻挡层的第三部分到形成用于P沟道器件的源极和漏极的P +区域，形成具有作为离子屏障的P沟道器件的给定功函数的第一控制电极，然后在具有N沟道源极和漏极区域的N沟道源极和漏极区域之间形成第二控制电极，与第一控制电极不同的功函数。

5. 发明授权

US4527325A Process for fabricating semiconductor devices utilizing a protective film during high temperature annealing 失效
标题翻译：在高温退火过程中制造利用保护膜的半导体器件的工艺
公开(公告)号：US4527325A
公开(公告)日：1985-07-09
申请号：US564880
申请日：1983-12-23
申请人： Henry J. Geipel, Jr. , Charles A. Schaefer , Francis R. White , John M. Wursthorn
发明人： Henry J. Geipel, Jr. , Charles A. Schaefer , Francis R. White , John M. Wursthorn
IPC分类号： H01L21/22 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/321 , H01L21/324 , H01L21/265 , H01L21/31
CPC分类号： H01L21/324 , H01L21/3145 , H01L21/32105 , Y10S438/911
摘要： A process is provided for fabricating a semiconductor structure wherein the structure has to be exposed to certain oxidizing conditions during certain of its processing steps, such as its high temperature annealing in an oxidizing ambient. It includes depositing a "sacrificial" layer, such as silicon, to provide a uniformly oxidizing surface during subsequent annealing operations. This sacrificial layer, which oxidizes uniformly, produces an oxide layer which also etches uniformly. Thus, after the annealing is completed, the surface oxide is removed through etching and the sacrificial layer is then also removed through a different etching step.
摘要翻译：提供了一种用于制造半导体结构的方法，其中该结构必须在其某些处理步骤中暴露于某些氧化条件，例如其在氧化环境中的高温退火。其包括沉积诸如硅的“牺牲”层，以在随后的退火操作期间提供均匀氧化的表面。这种氧化均匀的牺牲层产生也均匀蚀刻的氧化物层。因此，退火完成后，通过蚀刻去除表面氧化物，然后通过不同的蚀刻步骤除去牺牲层。

6. 发明授权

US4282646A Method of making a transistor array 失效
标题翻译：制造晶体管阵列的方法
公开(公告)号：US4282646A
公开(公告)日：1981-08-11
申请号：US68282
申请日：1979-08-20
申请人： Andres G. Fortino , Henry J. Geipel, Jr. , Lawrence G. Heller , Ronald Silverman
发明人： Andres G. Fortino , Henry J. Geipel, Jr. , Lawrence G. Heller , Ronald Silverman
IPC分类号： H01L21/822 , G11C11/56 , G11C17/12 , H01L21/225 , H01L21/8246 , H01L27/04 , H01L27/112 , H01L29/78 , H01L21/26
CPC分类号： H01L27/11266 , G11C11/56 , G11C11/5692 , G11C17/12 , H01L21/2253 , H01L27/112
摘要： A method of making a transistor array includes forming a plurality of gate electrodes insulated from a semiconductor substrate having an impurity of a given conductivity, introducing a first impurity having a conductivity opposite to that of the given conductivity into a given region of the substrate which is adjacent to an edge of each of the gate electrodes, introducing a second impurity having the given conductivity into given regions adjacent to selected gate electrodes, the second impurity having a significantly higher diffusivity than that of the first impurity in the semiconductor substrate, and driving the second impurity along the surface of the semiconductor substrate to form in the substrate under each of the selected gate electrodes a region having a concentration of impurity of the given conductivity higher than that of the semiconductor substrate. The transistor array may be used, e.g. to make a read only memory (ROM) by connecting appropriate current sensing means to each of the given regions to indicate the presence or absence of the higher diffusivity impurity when a predetermined voltage is applied to the gate electrodes. In one embodiment, the semiconductor substrate is made of P type conductivity, the first impurity is arsenic which produces N type conductivity regions and the second impurity is boron, which produces P type conductivity. Since boron has a higher diffusivity than arsenic, after they are driven by heating the boron impurity produces a high threshold region under the gate electrode when introduced in sufficiently high concentration.
摘要翻译：制造晶体管阵列的方法包括形成与具有给定导电性的杂质的半导体衬底绝缘的多个栅电极，将具有与所述导电性相反的导电性的第一杂质引入衬底的给定区域与每个栅电极的边缘相邻，将具有给定导电性的第二杂质引入到与所选择的栅电极相邻的给定区域中，第二杂质具有比半导体衬底中的第一杂质显着更高的扩散率，并驱动沿着半导体衬底的表面形成第二杂质，以在所选择的栅电极的每一个下的衬底中形成具有比半导体衬底的导电性高的给定导电性的杂质浓度的区域。可以使用晶体管阵列，例如，通过将适当的电流感测装置连接到每个给定区域来形成只读存储器（ROM），以指示当将预定电压施加到栅电极时存在或不存在较高扩散性杂质。在一个实施例中，半导体衬底由P型导电性制成，第一杂质是产生N型导电区域的砷，第二杂质是硼，产生P型导电性。由于硼具有比砷更高的扩散性，因此通过加热驱动硼杂质，当以足够高的浓度引入时，在栅电极下产生高阈值区域。

7. 发明授权

US4398341A Method of fabricating a highly conductive structure 失效
标题翻译：制造高导电结构的方法
公开(公告)号：US4398341A
公开(公告)日：1983-08-16
申请号：US304436
申请日：1981-09-21
申请人： Henry J. Geipel, Jr. , Larry A. Nesbit
发明人： Henry J. Geipel, Jr. , Larry A. Nesbit
IPC分类号： H01L29/78 , H01L21/027 , H01L21/28 , H01L21/3205 , H01L21/321 , H01L21/768 , H01L23/52 , H01L29/423 , H01L29/43 , H01L29/49 , H01L21/285
CPC分类号： H01L21/0272 , H01L21/28097 , H01L21/28123 , H01L21/321 , H01L21/7688 , H01L21/76889 , Y10S438/951
摘要： An improved method of fabricating a silicide structure includes depositing a metal, e.g., molybdenum or tungsten, directly onto a thin insulating layer of silicon dioxide and/or silicon nitride formed on a semiconductor substrate, co-depositing the metal and silicon onto the metal layer and then depositing silicon onto the co-deposited metal-silicon layer. This structure is annealed at a temperature sufficient to form a metal silicide between the thin insulating layer and the layer of silicon. The silicon layer serves as a source of silicon for the metal layer which is consumed during the annealing step to form, along with the co-deposited metal-silicon layer, a relatively thick metal silicide layer directly on the thin silicon dioxide layer. A sufficiently thick silicon layer is initially provided on the co-deposited metal-silicon layer so that a portion of the initial silicon layer remains after the annealing step has been completed. This excess silicon may be oxidized to form a passivating layer on top of the thick metal silicide layer. If all or a part of the silicon in the remaining silicon layer after annealing is removed, the thick metal silicide layer may be exposed to an oxidizing ambient for self-passivation. In this latter instance, the pure metal precipitates in the silicide resulting in a line with even greater conductivity than a pure silicide line, which is very desirable for interconnections.
摘要翻译：制造硅化物结构的改进方法包括将金属（例如钼或钨）直接沉积到半导体衬底上形成的二氧化硅和/或氮化硅的薄绝缘层上，将金属和硅共沉积到金属层上然后在共沉积的金属硅层上沉积硅。该结构在足以在薄绝缘层和硅层之间形成金属硅化物的温度下退火。硅层用作用于金属层的硅源，其在退火步骤期间消耗，以与共沉积的金属硅层一起形成直接在薄二氧化硅层上的相对厚的金属硅化物层。最初在共沉积的金属 - 硅层上提供足够厚的硅层，使得在退火步骤完成之后残留初始硅层的一部分。该多余的硅可被氧化以在厚金属硅化物层的顶部形成钝化层。如果除去退火后剩余硅层中的全部或部分硅，则可将厚金属硅化物层暴露于氧化环境以进行自钝化。在后一种情况下，纯金属在硅化物中沉淀，导致比纯硅化物线更好的导电性的线，这对于互连是非常需要的。

8. 发明授权

US4329773A Method of making low leakage shallow junction IGFET devices 失效
标题翻译：制造低泄漏浅结IGFET器件的方法
公开(公告)号：US4329773A
公开(公告)日：1982-05-18
申请号：US214940
申请日：1980-12-10
申请人： Henry J. Geipel, Jr. , Richard B. Shasteen
发明人： Henry J. Geipel, Jr. , Richard B. Shasteen
IPC分类号： H01L29/78 , H01L21/033 , H01L21/265 , H01L21/324 , H01L29/08 , H01L21/22 , H01L21/26
CPC分类号： H01L21/033 , H01L21/2652 , H01L21/324 , H01L29/0847
摘要： A method for forming shallow low leakage ion implanted source/drain regions in an integrated circuit environment including semirecessed oxide isolation regions in which high parasitic device threshold voltages are provided by an oxidizing/annealing post implant process. Arsenic ions are implanted into a recessed oxide isolated substrate followed by a wet oxidation process and a non-oxidizing annealing process for a period of time to provide a passivating dielectric over low leakage source/drain regions of less than one micron junction depth and to provide adequate high temperature annealing to reduce the charge effects in the oxide isolation regions caused by the implanted arsenic ions.
摘要翻译：一种在集成电路环境中形成浅的低泄漏离子注入源极/漏极区域的方法，包括半导体氧化物隔离区域，其中通过氧化/退火后植入工艺提供高寄生器件阈值电压。将砷离子注入到凹陷氧化物隔离衬底中，接着进行湿式氧化工艺和非氧化退火工艺一段时间，以在小于1微米结深度的低漏源/漏极区域上提供钝化电介质，并提供足够的高温退火以减少由注入的砷离子引起的氧化物隔离区域的电荷效应。

9. 发明授权

US4631219A Growth of bird's beak free semi-rox 失效
标题翻译：鸟喙自由半生长的增长
公开(公告)号：US4631219A
公开(公告)日：1986-12-23
申请号：US696824
申请日：1985-01-31
申请人： Henry J. Geipel, Jr. , Pai-Hung Pan
发明人： Henry J. Geipel, Jr. , Pai-Hung Pan
IPC分类号： H01L21/76 , H01L21/314 , H01L21/316 , H01L21/32 , H01L21/762 , B32B15/04
CPC分类号： H01L21/76202 , H01L21/3144 , H01L21/32 , Y10T428/24273 , Y10T428/24322 , Y10T428/24777
摘要： An oxygen-impervious pad structure which reduces the bird's beak profiles in semi-recessed oxide isolation regions. The sidewalls of a conventional silicon oxide - silicon nitride pad are coated with a thick layer of oxynitride. A thin layer of oxynitride is grown on the substrate surface prior to deposition of the thick oxynitride layer. The thick oxynitride layer prevents lateral oxidizing specie diffusion through the oxide layer of the conventional pad, and the thin oxynitride layer prevents lateral oxidizing specie diffusion through the pad-substrate interface into the substrate region beneath the pad.
摘要翻译：一种不透氧的垫结构，可减少半凹陷氧化物隔离区域中的鸟嘴形貌。常规氧化硅 - 氮化硅垫的侧壁涂覆有厚氮氧化物层。在沉积厚氮氧化物层之前，在衬底表面上生长薄氮氧化物。厚氧氮化物层防止横向氧化物质扩散通过常规焊盘的氧化物层，并且薄氧氮化物层防止横向氧化物质通过焊盘 - 衬底界面扩散到焊盘下方的衬底区域中。

10. 发明授权

US4622573A CMOS contacting structure having degeneratively doped regions for the prevention of latch-up 失效
标题翻译： CMOS接触结构具有退化掺杂区域，以防止闩锁
公开(公告)号：US4622573A
公开(公告)日：1986-11-11
申请号：US831098
申请日：1986-02-18
申请人： Paul E. Bakeman, Jr. , Henry J. Geipel, Jr.
发明人： Paul E. Bakeman, Jr. , Henry J. Geipel, Jr.
IPC分类号： H01L27/092 , H01L29/08 , H01L29/45 , H01L29/78 , H01L29/88
CPC分类号： H01L29/456 , H01L27/0921 , H01L29/0847
摘要： A contact structure suitable for use in a CMOS device to prevent or suppress the latch-up phenomenon in the device. It uses two degeneratively doped regions of different conductivity type with a tunnel injecting interface therebetween and a conductive segment contiguous to one of the two regions. Using such a structure as the source of an FET in a CMOS arrangement causes the emitter area and the base spreading resistance of the corresponding parasitic bipolar transistor to be reduced. This in turn causes the current gain of the parasitic transistor to decrease and the latch-up phenomenon to be prevented or suppressed.
摘要翻译：适用于CMOS器件的接触结构，以防止或抑制器件中的闭锁现象。它使用具有不同导电类型的两个退化掺杂区域，其间具有隧道注入界面和与两个区域之一相邻的导电段。使用CMOS布置中的FET的源极这样的结构使得相应的寄生双极晶体管的发射极面积和基极扩展电阻降低。这又导致寄生晶体管的电流增益减小，并且可以防止或抑制闩锁现象。

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