专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06665787B2 Very high speed page operations in indirect accessed memory systems 失效
公开(公告)号：US06665787B2
公开(公告)日：2003-12-16
申请号：US09795414
申请日：2001-02-28
申请人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith, III , Robert B. Tremaine , Michael Wazlowski
发明人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith, III , Robert B. Tremaine , Michael Wazlowski
IPC分类号： G06F1208
CPC分类号： G06F12/1009
摘要： A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a translation table structure in the physical memory storage having entries for associating a real address with sectors of the physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, the table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by the processor; and, a control device for directly manipulating entries in the translation table structure for performing page operations without actually accessing physical memory data contents. In this system, the actual data of the pages involved in the operation are never accessed by the processor and therefore is never required in the memory cache hierarchy, thus eliminating the cache damage normally associated with these block operations. Further the manipulation of the translation table will involve reading and writing a few bytes to perform the operation as opposed to reading and writing the hundreds or thousands of bytes in the pages being manipulated.

2. 发明授权

US06549995B1 Compressor system memory organization and method for low latency access to uncompressed memory regions 失效
标题翻译：用于低延迟访问未压缩存储器区域的压缩机系统存储器组织和方法
公开(公告)号：US06549995B1
公开(公告)日：2003-04-15
申请号：US09478557
申请日：2000-01-06
申请人： Charles O. Schulz , T. Basil Smith, III , Robert B. Tremaine , Michael Wazlowski
发明人： Charles O. Schulz , T. Basil Smith, III , Robert B. Tremaine , Michael Wazlowski
IPC分类号： G06F1200
CPC分类号： G06F12/08 , G06F12/0292 , G06F2212/401
摘要： In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies and, wherein information stored within the main memory is indirectly accessible by a processor through a compression and decompression mechanisms, an improved memory architecture that accommodates the necessary compressed information data structures, together with a memory region and mapping method for storing information that bypasses the compression and decompression mechanisms to provide low latency processor access to certain address spaces.
摘要翻译：在具有主存储器的处理系统中，其中以压缩格式存储信息，以通过压缩效率获得额外的存储，并且其中存储在主存储器内的信息可由处理器通过压缩和解压缩机制间接访问，改进的存储器架构，其容纳必要的压缩信息数据结构，以及存储器区域和映射方法，用于存储绕过压缩和解压缩机制的信息，以提供对某些地址空间的低延迟处理器访问。

3. 发明授权

US07523290B2 Very high speed page operations in indirect accessed memory systems 有权
标题翻译：间接访问存储系统中的高速页面操作
公开(公告)号：US07523290B2
公开(公告)日：2009-04-21
申请号：US10672376
申请日：2003-09-26
申请人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith , Robert B. Tremaine , Michael Wazlowski
发明人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith , Robert B. Tremaine , Michael Wazlowski
IPC分类号： G06F12/00
CPC分类号： G06F12/1009
摘要： A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a translation table structure in the physical memory storage having entries for associating a real address with sectors of the physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, the table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by the processor; and, a control device for directly manipulating entries in the translation table structure for performing page operations without actually accessing physical memory data contents. In this system, the actual data of the pages involved in the operation are never accessed by the processor and therefore is never required in the memory cache hierarchy, thus eliminating the cache damage normally associated with these block operations. Further the manipulation of the translation table will involve reading and writing a few bytes to perform the operation as opposed to reading and writing the hundreds or thousands of bytes in the pages being manipulated.
摘要翻译：一种计算系统和方法，所述计算系统和方法采用处理器设备来生成与实际存储器系统的存储器位置相关联的用于读取和写入数据的实际地址，所述系统包括：所述实际存储器系统中的用于存储数据的多个存储块，用于存储包括一个或多个实际存储器块的数据页面的存储器存储器，每个实际存储器块被划分成一个或多个扇区，每个扇区包括物理存储器的连续字节; 物理存储器存储器中的转换表结构具有用于将实际地址与物理存储器的扇区相关联的条目，每个转换表条目包括用于指向其相关联的实际存储器块中的对应扇区的一个或多个指针，用于由处理器发起的用于存储器读和写操作的一个或多个分配扇区中的数据; 以及用于直接操纵翻译表结构中的条目以执行页面操作而不实际访问物理存储器数据内容的控制装置。在该系统中，操作所涉及的页面的实际数据从不被处理器访问，因此在存储器高速缓存层次结构中从不需要这样的数据，从而消除通常与这些块操作相关联的高速缓存损坏。此外，翻译表的操作将涉及读取和写入几个字节以执行操作，而不是在被操纵的页面中读取和写入数百或数千字节。

4. 发明授权

US06446145B1 Computer memory compression abort and bypass mechanism when cache write back buffer is full 失效
标题翻译：当缓存回写缓冲区已满时，计算机内存压缩中止和旁路机制
公开(公告)号：US06446145B1
公开(公告)日：2002-09-03
申请号：US09478556
申请日：2000-01-06
申请人： David Har , Charles O. Schulz , Robert B. Tremaine
发明人： David Har , Charles O. Schulz , Robert B. Tremaine
IPC分类号： G06F1300
CPC分类号： G06F12/08 , G06F12/0804 , G06F2212/401
摘要： In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies, a method and apparatus for enabling termination of a pending compression operation for the purpose of writing the data directly to the main memory, bypassing the compressor hardware during stall conditions. Memory space (compressibility) is sacrificed for higher system performance during these temporary write back stall events. A background memory scrub later detects and recovers the “lost” compressibility by recycling the uncompressed data back through the compressor during idle periods.
摘要翻译：在具有主存储器的处理系统中，其中以压缩格式存储信息以便通过压缩效率获得额外的存储的方法和装置，用于终止待处理的压缩操作以将数据直接写入主要的方法和装置存储器，在失速条件下绕过压缩机硬件。在这些临时回写失速事件期间，为了提高系统性能，牺牲了内存空间（可压缩性）。后台存储器擦除后来通过在空闲期间将压缩后的数据再循环通过压缩器来检测并恢复“丢失”可压缩性。

5. 发明授权

US08806177B2 Prefetch engine based translation prefetching 有权
标题翻译：预取引擎基于翻译预取
公开(公告)号：US08806177B2
公开(公告)日：2014-08-12
申请号：US11482222
申请日：2006-07-07
申请人： Orran Y. Krieger , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0862 , G06F2212/6028 , G06F2212/651 , G06F2212/654
摘要： A method and system for prefetching in computer system are provided. The method in one aspect includes using a prefetch engine to perform prefetch instructions and to translate unmapped data. Misses to address translations during the prefetch are handled and resolved. The method also includes storing the resolved translations in a respective cache translation table. A system for prefetching in one aspect includes a prefetch engine operable to receive instructions to prefetch data from the main memory. The prefetch engine is also operable to search cache address translation for prefetch data and perform address mapping translation, if the prefetch data is unmapped. The prefetch engine is further operable to prefetch the data and store the address mapping in one or more cache memory, if the data is unmapped.
摘要翻译：提供了一种在计算机系统中预取的方法和系统。该方法在一个方面包括使用预取引擎来执行预取指令并转换未映射的数据。在预取期间解决翻译错误的处理和解决。该方法还包括将分辨的翻译存储在相应的缓存转换表中。用于在一个方面预取的系统包括预取引擎，其可操作以接收从主存储器预取数据的指令。如果预取数据未被映射，则预取引擎还可用于搜索缓存地址转换以获取预取数据并执行地址映射转换。如果数据未被映射，则预取引擎还可操作以预取数据并将地址映射存储在一个或多个高速缓冲存储器中。

6. 发明授权

US08674856B2 Data compression utilizing longest common subsequence template 失效
标题翻译：使用最长公共子序列模板的数据压缩
公开(公告)号：US08674856B2
公开(公告)日：2014-03-18
申请号：US13587669
申请日：2012-08-16
申请人： Kanak B. Agarwal , Damir A. Jamsek , Michael A. Paolini , Robert B. Tremaine
发明人： Kanak B. Agarwal , Damir A. Jamsek , Michael A. Paolini , Robert B. Tremaine
IPC分类号： H03M7/34
CPC分类号： H03M7/30 , H03M7/607
摘要： In response to receipt of an input string, an attempt is made to identify, in a template store, a closely matching template for use as a compression template. In response to identification of a closely matching template that can be used as a compression template, the input string is compressed into a compressed string by reference to a longest common subsequence compression template. Compressing the input string includes encoding, in a compressed string, an identifier of the compression template, encoding substrings of the input string not having commonality with the compression template of at least a predetermined length as literals, and encoding substrings of the input string having commonality with the compression template of at least the predetermined length as a jump distance without reference to a base location in the compression template. The compressed string is then output.
摘要翻译：响应于输入字符串的接收，尝试在模板存储器中识别紧密匹配的模板以用作压缩模板。响应于可以用作压缩模板的紧密匹配的模板的识别，通过参考最长的公共子序列压缩模板将输入字符串压缩成压缩字符串。压缩输入字符串包括在压缩字符串中编码压缩模板的标识符，将与压缩模板具有至少预定长度的压缩模板不一致的输入字符串的子串编码为文字，以及编码具有共同性的输入字符串的子串至少具有预定长度的压缩模板作为跳跃距离，而不参考压缩模板中的基本位置。然后输出压缩字符串。

7. 发明授权

US08513972B2 Soft error resilient FPGA 失效
公开(公告)号：US08513972B2
公开(公告)日：2013-08-20
申请号：US13352900
申请日：2012-01-18
申请人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
发明人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H03K19/17764
摘要： A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

8. 发明申请

US20120023300A1 MEMORY PAGE MANAGEMENT IN A TIERED MEMORY SYSTEM 有权
标题翻译：一个层次化的记忆系统中的存储页面管理
公开(公告)号：US20120023300A1
公开(公告)日：2012-01-26
申请号：US12843718
申请日：2010-07-26
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/16 , G06F12/14
CPC分类号： G06F12/1009 , G06F11/3471 , G06F12/1475 , G06F2201/88
摘要： Memory page management in a tiered memory system including a system that includes at least one page table for storing a plurality of entries, each entry associated with a page of memory and each entry including an address of the page and a memory tier of the page. The system also includes a control program configured for allocating pages associated with the entries to a software module, the allocated pages from at least two different memory tiers. The system further includes an agent of the control program capable of operating independently of the control program, the agent configured for receiving an authorization key to the allocated pages, and for migrating the allocated pages between the different memory tiers responsive to the authorization key.
摘要翻译：包括包括至少一个用于存储多个条目的页表的系统的系统中的存储器页面管理，每个条目与存储器页面相关联，每个条目包括页面的地址和页面的存储器层。该系统还包括配置用于将与条目相关联的页面分配给软件模块的控制程序，来自至少两个不同存储器层的所分配的页面。该系统还包括能够独立于控制程序操作的控制程序的代理，被配置为接收对所分配的页面的授权密钥的代理，以及响应于授权密钥在不同存储器层之间迁移分配的页面。

9. 发明申请

US20110161597A1 Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller 审中-公开
标题翻译：组合内存包括通过IO控制器访问的存储内存中的逻辑分区
公开(公告)号：US20110161597A1
公开(公告)日：2011-06-30
申请号：US12649856
申请日：2009-12-30
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0895
摘要： A computer system having a combined memory. A first logical partition of the combined memory is a main memory region in a storage memory. A second logical partition of the combined memory is a direct memory region in a main memory. A memory controller comprising a storage controller is configured to receive a memory access request including a real address from a processor, determine whether the real address is for the first logical partition or for the second logical partition. If the address is for the first logical partition the storage controller communicates with an IO controller in the storage memory to service the memory access request. If the address is for the direct memory region, the memory controller services the memory access request in a conventional manner.
摘要翻译：具有组合存储器的计算机系统。组合存储器的第一逻辑分区是存储存储器中的主存储器区域。组合存储器的第二逻辑分区是主存储器中的直接存储器区域。包括存储控制器的存储器控制器被配置为从处理器接收包括实际地址的存储器访问请求，确定实际地址是为第一逻辑分区还是用于第二逻辑分区。如果地址是用于第一逻辑分区，则存储控制器与存储器中的IO控制器通信以服务存储器访问请求。如果地址用于直接存储区域，则存储器控制器以常规方式服务存储器访问请求。

10. 发明申请

US20110087834A1 Memory Package Utilizing At Least Two Types of Memories 有权
标题翻译：记忆包利用至少两种类型的记忆
公开(公告)号：US20110087834A1
公开(公告)日：2011-04-14
申请号：US12576028
申请日：2009-10-08
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/16 , G06F12/02
CPC分类号： G06F12/0638 , Y10S707/99931
摘要： A memory system and methods for memory manage are presented. The memory system includes a volatile memory electrically connected to a high-density memory; a memory controller that expects data to be written or read to or from the memory system at a bandwidth and a latency associated with the volatile memory; a directory within the volatile memory that associates a volatile memory address with data stored in the high-density memory; and redundant storage in the high-density memory that stores a copy of the association between the volatile memory address and the data stored in the high-density memory. The methods for memory management allow writing to and reading from the memory system using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).
摘要翻译：介绍了一种存储器系统和存储器管理方法。存储器系统包括电连接到高密度存储器的易失性存储器; 期望以与易失性存储器相关联的带宽和等待时间从存储器系统写入或读取数据的存储器控制器; 易失性存储器内的目录，其将易失性存储器地址与存储在高密度存储器中的数据相关联; 以及高密度存储器中的冗余存储器，其存储易失性存储器地址和存储在高密度存储器中的数据之间的关联的副本。用于存储器管理的方法允许使用第一存储器读/写接口（例如DRAM接口等）从存储器系统进行写入和读取，尽管数据存储在不同存储器类型（例如FLASH等）的器件中，。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式