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1. 发明申请

US20100148277A1 ISOLATED METAL PLUG PROCESS FOR USE IN FABRICATING CARBON NANOTUBE MEMORY CELLS 失效
标题翻译：用于制备碳纳米管存储器细胞的隔离金属压片方法
公开(公告)号：US20100148277A1
公开(公告)日：2010-06-17
申请号：US12710477
申请日：2010-02-23
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Thomas Rueckes , Claude L. Bertin
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Thomas Rueckes , Claude L. Bertin
IPC分类号： H01L27/112
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译：本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。纳米管横杆元件布置成跨越下室。第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。

2. 发明授权

US07824946B1 Isolated metal plug process for use in fabricating carbon nanotube memory cells 有权
标题翻译：用于制造碳纳米管记忆单元的隔离金属塞工艺
公开(公告)号：US07824946B1
公开(公告)日：2010-11-02
申请号：US11429069
申请日：2006-05-05
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Claude L. Bertin , Thomas Rueckes
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Claude L. Bertin , Thomas Rueckes
IPC分类号： H01L21/00 , H01L21/64
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译：本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。纳米管横杆元件布置成跨越下室。第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。

3. 发明授权

US07884430B2 Isolated metal plug process for use in fabricating carbon nanotube memory cells 失效
标题翻译：用于制造碳纳米管记忆单元的隔离金属塞工艺
公开(公告)号：US07884430B2
公开(公告)日：2011-02-08
申请号：US12710477
申请日：2010-02-23
申请人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Thomas Rueckes , Claude L. Bertin
发明人： Richard J. Carter , Peter A. Burke , Verne C. Hornback , Thomas Rueckes , Claude L. Bertin
IPC分类号： H01L29/84
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译：本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。纳米管横杆元件布置成跨越下室。第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。

4. 发明授权

US07928521B1 Non-tensioned carbon nanotube switch design and process for making same 有权
标题翻译：非张力碳纳米管开关的设计与制造过程
公开(公告)号：US07928521B1
公开(公告)日：2011-04-19
申请号：US11142725
申请日：2005-05-31
申请人： Peter A. Burke , Thomas Rueckes , Claude L. Bertin
发明人： Peter A. Burke , Thomas Rueckes , Claude L. Bertin
IPC分类号： H01L29/82
CPC分类号： H01H1/0094 , B82Y10/00 , H01H59/0009 , H01H2001/0042 , H01H2059/0045 , H01L51/0048 , H01L51/0591 , Y10S977/932
摘要： The invention comprises a carbon nanotube switch suitable for use in an integrated circuit structure and capable of being moved from a first position in a first plane in the switch to a second position in a second plane in the switch using approximately the same energy as required to move the switch from the second position back to the first position. The switch comprises a flexible carbon nanotube strip secured clamped at one end in a first plane in a switching chamber, and secured or clamped, at the opposite end of the carbon nanotube, in a second plane in the switching chamber, which is parallel to the first plane but spaced therefrom, to permit the central portion of the carbon nanotube strip to move in the chamber between a first position in the first plane and in electrical contact with one or more first electrodes and a second position in the second plane and in electrical contact with one or more second electrodes.
摘要翻译：本发明包括一种适用于集成电路结构的碳纳米管开关，其能够使用开关中的第一平面中的第一位置移动到开关中的第二平面中的第二位置，使用大约相同的能量将开关从第二个位置移回到第一个位置。开关包括柔性碳纳米管条，其固定在切换室中的第一平面中的一端处夹持，并且在碳纳米管的相对端处固定或夹紧在开关室中的平行于第二平面的第二平面中第一平面但与其间隔开，以允许碳纳米管条的中心部分在室中在第一平面中的第一位置和与一个或多个第一电极电连接并且在第二平面中的第二位置和电气与一个或多个第二电极接触。

5. 发明授权

US08552535B2 Trench shielding structure for semiconductor device and method 有权
标题翻译：半导体器件的沟槽屏蔽结构及方法
公开(公告)号：US08552535B2
公开(公告)日：2013-10-08
申请号：US12271068
申请日：2008-11-14
申请人： Peter A. Burke , Brian Pratt , Prasad Venkatraman
发明人： Peter A. Burke , Brian Pratt , Prasad Venkatraman
IPC分类号： H01L29/66
CPC分类号： H01L29/4236 , H01L29/0696 , H01L29/401 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/4933 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.
摘要翻译：用于半导体器件的屏蔽结构包括多个沟槽。沟槽包括形成在其中的钝化衬垫和屏蔽电极。在一个实施例中，屏蔽结构位于控制板下方。在另一个实施例中，屏蔽结构放置在控制转轮下方。

6. 发明授权

US08410578B2 Method of manufacturing a semiconductor component and structure 有权
标题翻译：制造半导体元件和结构的方法
公开(公告)号：US08410578B2
公开(公告)日：2013-04-02
申请号：US12962579
申请日：2010-12-07
申请人： Sallie Hose , Peter A. Burke , Li Jiang , Sudhama C. Shastri
发明人： Sallie Hose , Peter A. Burke , Li Jiang , Sudhama C. Shastri
IPC分类号： H01L29/94 , H01L21/02 , H01L21/768
CPC分类号： H01L23/5227 , H01L23/5223 , H01L23/5228 , H01L23/53238 , H01L24/05 , H01L27/0629 , H01L28/10 , H01L28/24 , H01L28/40 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/12035 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated passive device. In accordance with embodiments, the monolithically integrated passive device includes an inductor formed from damascene structures.
摘要翻译：一种半导体元件及其制造方法，该半导体元件包括单片集成无源器件。根据实施例，单片集成无源器件包括由镶嵌结构形成的电感器。

7. 发明申请

US20120326227A1 METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE AND STRUCTURE 有权
标题翻译：制造绝缘栅半导体器件和结构的方法
公开(公告)号：US20120326227A1
公开(公告)日：2012-12-27
申请号：US13170033
申请日：2011-06-27
申请人： Peter A. Burke , Gordon M. Grivna , Balaji Padmanabhan , Prasad Venkatraman
发明人： Peter A. Burke , Gordon M. Grivna , Balaji Padmanabhan , Prasad Venkatraman
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/4933 , H01L29/66348 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7827
摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.
摘要翻译：在一个实施例中，垂直绝缘栅场效应晶体管包括形成在半导体材料内的沟槽结构中的屏蔽电极。栅电极使用栅极绝缘层与半导体材料隔离。在形成屏蔽电极之前，间隔层可以沿沟槽结构的部分形成屏蔽绝缘层。屏蔽绝缘层比栅极绝缘层厚。在另一个实施例中，屏蔽绝缘层具有可变的厚度。

8. 发明申请

US20110052449A1 DEVICE FOR AERATING A REGION AFTER INJECTION WITH VAPORIZED HYDROGEN PEROXIDE 有权
标题翻译：用过氧化氢过滤注入一个地区的装置
公开(公告)号：US20110052449A1
公开(公告)日：2011-03-03
申请号：US12939246
申请日：2010-11-04
申请人： Michael A. Centanni , Peter A. Burke
发明人： Michael A. Centanni , Peter A. Burke
IPC分类号： A62B7/08
CPC分类号： A61L2/208 , A61L2/202 , A61L2/206 , A61L9/015 , A61L2202/13
摘要： A method and apparatus for aerating a region exposed to a gaseous/vaporous sterilant. A catalytic destroyer and a reactive chemical unit are used to reduce the concentration of the gaseous/vaporous sterilant within the region. The reactive chemical unit includes a chemistry that is chemically reactive with the gaseous/vaporous sterilant. In one embodiment, the gaseous/vaporous sterilant is vaporized hydrogen peroxide and the chemistry of the reactive chemical unit includes thiosulfate and iodide.
摘要翻译：用于对暴露于气体/蒸气灭菌剂的区域进行曝气的方法和装置。催化破坏剂和反应性化学单元用于降低该区域内气态/蒸气灭菌剂的浓度。反应性化学单元包括与气态/蒸气灭菌剂化学反应的化学物质。在一个实施方案中，气态/蒸气灭菌剂是蒸发的过氧化氢，并且反应性化学单元的化学性质包括硫代硫酸盐和碘化物。

9. 发明授权

US07829426B2 Semiconductor component and method of manufacture 有权
标题翻译：半导体元件及制造方法
公开(公告)号：US07829426B2
公开(公告)日：2010-11-09
申请号：US12549100
申请日：2009-08-27
申请人： Peter A. Burke , Sallie Hose , Sudhama C. Shastri
发明人： Peter A. Burke , Sallie Hose , Sudhama C. Shastri
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L21/76801 , H01L21/76807 , H01L21/76846 , H01L23/5227 , H01L23/5228 , H01L23/53238 , H01L28/20 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.
摘要翻译：一种包括集成无源器件的半导体部件和用于制造半导体部件的方法。在衬底上方制造垂直集成的无源器件。根据一个实施例，在基板上方的第一电平中制造电阻器，在垂直于第一电平的第二电平上制造电容器，并且在垂直于第二电平的第三电平上制造铜电感器水平。电容器有铝板。根据另一个实施例，在基板上方的第一电平中制造电阻器，在垂直于第一电平的第二电平上制造铜电感器，并且制造在垂直于第二电平的第三电平的电容器水平。电容器可以具有铝板，或者铜电感器的一部分可以用作其板之一。

10. 发明申请

US20100200993A1 DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES 有权
标题翻译：用于增加铜互连结构中电磁寿命的电介质障碍层
公开(公告)号：US20100200993A1
公开(公告)日：2010-08-12
申请号：US12764004
申请日：2010-04-20
申请人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
发明人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
IPC分类号： H01L23/532 , H01L21/31
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76826 , H01L21/76834 , H01L21/76883
摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.
摘要翻译：本发明的实施例包括具有增加的电迁移寿命的铜互连结构。这种结构可以包括其上形成有铜层的半导体衬底。在铜层上形成介电阻挡层叠体。电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改善的对铜的粘合性，并且两个部分形成为具有耐铜扩散性。本发明还包括用于构造这种结构的几个实施例。可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

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