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1. 发明申请

US20070253517A1 Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权
标题翻译：用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量
公开(公告)号：US20070253517A1
公开(公告)日：2007-11-01
申请号：US11414521
申请日：2006-04-28
申请人： Pervez Aziz , Gregory Sheets , Vladimir Sindalovsky
发明人： Pervez Aziz , Gregory Sheets , Vladimir Sindalovsky
IPC分类号： H03D3/24
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译：提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。

2. 发明申请

US20070195874A1 Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data 有权
标题翻译：用于使用DFE检测数据为判决反馈均衡器生成一个或多个时钟信号的方法和装置
公开(公告)号：US20070195874A1
公开(公告)日：2007-08-23
申请号：US11356691
申请日：2006-02-17
申请人： Pervez Aziz , Gregory Sheets , Lane Smith
发明人： Pervez Aziz , Gregory Sheets , Lane Smith
IPC分类号： H03H7/30 , H04L7/00
CPC分类号： H04L7/0062 , H04L7/033 , H04L7/04 , H04L2025/0349
摘要： Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. In a multi-level implementation, the received signal is sampled using a clock associated with each of the levels and the samples are latched using a vertical slicing technique to generate DFE data associated with each of said levels.
摘要翻译：提供了用于使用DFE检测数据为判决反馈均衡器生成一个或多个时钟信号的方法和装置。使用数据时钟和转换时钟对接收到的信号进行采样，以分别产生数据采样信号和转换采样信号。为每个数据采样和转换采样信号获得DFE校正，以产生DFE检测数据和DFE转换数据。 DFE检测数据和DFE转换数据然后被施加到产生信号以调整数据时钟和转换时钟中的一个或多个的相位的相位检测器。在多级实现中，使用与每个级别相关联的时钟对接收到的信号进行采样，并且使用垂直限幅技术来锁存样本以生成与每个所述级别相关联的DFE数据。

3. 发明申请

US20050078758A1 Method for training a transceiver for high speed communications 有权
标题翻译：用于训练用于高速通信的收发器的方法
公开(公告)号：US20050078758A1
公开(公告)日：2005-04-14
申请号：US10964056
申请日：2004-10-12
申请人： Pervez Aziz , Donald Laturell , Mohammad Mobin , Gregory Sheets , Lane Smith
发明人： Pervez Aziz , Donald Laturell , Mohammad Mobin , Gregory Sheets , Lane Smith
IPC分类号： G01R31/317 , H04B3/00 , H04B3/04 , H04L25/03
CPC分类号： G01R31/31715 , H04B3/04 , H04L25/03038 , H04L2025/03356 , H04L2025/03477 , H04L2025/03617
摘要： In training a SERDES, a Common Electrical Interface (CEI) training frame, having certain bits of information embedded therein, is transmitted over a path which comprises transmitter, channel, and receiver components. The present invention analyzes the resulting received signal and determines the effective aggregate channel impulse response of these three components. The invention then determines an estimate of the inverse of this aggregate channel and uses this determination to reduce distortions that have been introduced into a signal that has been transmitted over the path.
摘要翻译：在训练SERDES时，通过包含发射机，信道和接收机组件的路径发送具有嵌入其中的某些信息位的公共电接口（CEI）训练帧。本发明分析所得到的接收信号并确定这三个分量的有效总信道脉冲响应。然后，本发明确定该聚合信道的逆的估计，并且使用该确定来减少已经被引入到已经通过该路径传输的信号中的失真。

4. 发明申请

US20070237275A1 Method and apparatus for a time domain zero phase start using binary sampled data 审中-公开
标题翻译：使用二进制采样数据的时域零相位开始的方法和装置
公开(公告)号：US20070237275A1
公开(公告)日：2007-10-11
申请号：US11399647
申请日：2006-04-06
申请人： Pervez Aziz , Gregory Sheets
发明人： Pervez Aziz , Gregory Sheets
IPC分类号： H04L7/00
CPC分类号： H04L7/042 , H04L7/10 , H04L2007/047
摘要： Methods and apparatus are provided for obtaining a phase offset estimate from a data stream. A binary sampled version of the data stream is obtained based on a clock. A first dot product of the binary sampled version of the data stream and an ideal sequence and a second dot product of the binary sampled version of the data stream and a delayed ideal sequence are accumulated. A phase offset of the clock is adjusted until the accumulated first and second dot product satisfy one or more predefined conditions. For example, the predefined conditions can comprise a transition of at least one of the accumulated first and second dot product or whether at least one of the accumulated first and second dot product transition to a final value.
摘要翻译：提供了用于从数据流获得相位偏移估计的方法和装置。基于时钟获得数据流的二进制采样版本。数据流的二进制采样版本和数据流的二进制采样版本和延迟的理想序列的理想序列和第二点积的第一点积积分。调整时钟的相位偏移，直到累积的第一和第二点积满足一个或多个预定条件。例如，预定条件可以包括累积的第一和第二点积中的至少一个的过渡，或者累积的第一和第二点积转换中的至少一个是否到最终值。

5. 发明申请

US20070206711A1 Method and apparatus for reducing latency in a clock and data recovery (CDR) circuit 有权
标题翻译：用于减少时钟和数据恢复（CDR）电路中的延迟的方法和装置
公开(公告)号：US20070206711A1
公开(公告)日：2007-09-06
申请号：US11367214
申请日：2006-03-03
申请人： Pervez Aziz , Gregory Sheets
发明人： Pervez Aziz , Gregory Sheets
IPC分类号： H03D3/24
CPC分类号： H03D13/003 , H03L7/081 , H03L7/0812 , H03L7/087 , H03L7/093 , H04L7/033
摘要： Disclosed is a system and method for a clock and data recovery (CDR) circuit. A phase selection circuit (PSC) generates a signal comprising frequency and phase. A voltage controlled oscillator (VCO) connected to the PSC generates a clock signal. The clock signal controls the frequency of the signal. The CDR circuit also includes a phase adjustment signal generator connected to the PSC for generating a phase adjustment signal. The phase adjustment signal controls the phase of the signal.
摘要翻译：公开了一种用于时钟和数据恢复（CDR）电路的系统和方法。相位选择电路（PSC）产生包括频率和相位的信号。连接到PSC的压控振荡器（VCO）产生时钟信号。时钟信号控制信号的频率。 CDR电路还包括连接到PSC的相位调整信号发生器，用于产生相位调整信号。相位调整信号控制信号的相位。

6. 发明申请

US20070189360A1 Method and apparatus for generation of asynchronous clock for spread spectrum transmission 有权
标题翻译：用于产生扩频传输的异步时钟的方法和装置
公开(公告)号：US20070189360A1
公开(公告)日：2007-08-16
申请号：US11353431
申请日：2006-02-14
申请人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , William Wilson , Craig Ziemer
发明人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , William Wilson , Craig Ziemer
IPC分类号： H03D3/24 , H03D1/00 , H03D3/18 , H04L27/06 , H04B1/00
CPC分类号： H04L27/0014 , H04B1/7075 , H04L2027/0036
摘要： A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.
摘要翻译：用于扩频率控制的电路使用第一内插器在第一信号和第二信号之间进行相位插值，并且基于第一控制信号产生第一输出信号。第二内插器用于在第三信号和第四信号之间进行相位插值，并且基于第二控制信号产生第二输出信号。多路复用器用于基于选择信号选择第一输出信号或第二输出信号作为扩频时钟（SSCLK）。跳跃内插器控制用于与SSCLK同步地产生基于第一类型的相位调整请求的第一控制信号，基于第二类型的相位调整请求的第二控制信号，以及选择信号在改变第一控制信号或第二控制信号之后允许内插器稳定时间之后，在第一输出信号和第二输出信号之间切换多路复用器。

7. 发明申请

US20070052460A1 Statically controlled clock source generator for VCDL clock phase trimming 失效
公开(公告)号：US20070052460A1
公开(公告)日：2007-03-08
申请号：US11221316
申请日：2005-09-07
申请人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
发明人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H04L7/0337
摘要： The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

8. 发明申请

US20060222123A1 Method and apparatus for monitoring a data eye in a clock and data recovery system 审中-公开
标题翻译：用于在时钟和数据恢复系统中监视数据眼的方法和装置
公开(公告)号：US20060222123A1
公开(公告)日：2006-10-05
申请号：US11095178
申请日：2005-03-31
申请人： Mohammad Mobin , Gregory Sheets , Lane Smith
发明人： Mohammad Mobin , Gregory Sheets , Lane Smith
IPC分类号： H04B1/10
CPC分类号： H04B17/309 , H04B17/23 , H04L7/0025
摘要： Methods and apparatus are provided for monitoring a data eye associated with a received signal. A plurality of samples of the received signal are obtained for each unit interval based on a clock recovered from the received signal, to obtain an estimate of the data eye. According to one aspect of the invention, the samples are obtained substantially simultaneous to a decoding of the received signal. The collected data eye samples can optionally be processed, for example, to collect statistics on the received signal or to determine a distribution of the received signal.
摘要翻译：提供了用于监视与接收信号相关联的数据眼的方法和装置。基于从接收信号恢复的时钟，针对每个单位间隔获得接收信号的多个样本，以获得数据眼睛的估计。根据本发明的一个方面，基本上与所接收信号的解码同时获得样本。收集的数据眼睛样本可以可选地被处理，例如，以收集关于接收到的信号的统计信息或确定接收信号的分布。

9. 发明申请

US20100219996A1 DC OFFSET DETECTION AND CORRECTION FOR USER TRAFFIC 有权
标题翻译： DC偏移检测和校正用户交通
公开(公告)号：US20100219996A1
公开(公告)日：2010-09-02
申请号：US12380639
申请日：2009-03-02
申请人： Christopher Abel , Mohammad Mobin , Robert Kapuschinsky , Lane Smith , Paul Tracy , Gregory Sheets
发明人： Christopher Abel , Mohammad Mobin , Robert Kapuschinsky , Lane Smith , Paul Tracy , Gregory Sheets
IPC分类号： H03M1/10
CPC分类号： H04L25/061
摘要： In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.
摘要翻译：在所描述的实施例中，采用例如时钟和数据恢复（CDR）的通信系统在输入数据流信号中检测并应用校正DC偏移，称为“DC偏移校准”。 DC偏移校准在输入电路（如输入放大器和检测锁存器）中对直流偏移进行静态校准，无输入数据，并在输入数据流运行期间对DC偏移进行统计校准，以校正直流电平的动态偏移。这种DC偏移校准使用用于检测DC偏移的输入数据流的数据眼睛测量，并施加相反的DC偏移以在实时业务期间维持相对平衡的数据眼睛。

10. 发明申请

US20070018694A1 HIGH-SPEED CML CIRCUIT DESIGN 有权
标题翻译：高速CML电路设计
公开(公告)号：US20070018694A1
公开(公告)日：2007-01-25
申请号：US11421675
申请日：2006-06-01
申请人： Jinghong Chen , Gregory Sheets , Lane Smith
发明人： Jinghong Chen , Gregory Sheets , Lane Smith
IPC分类号： H03K19/094
CPC分类号： H03K19/09432 , H03K19/01707
摘要： A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.
摘要翻译：提供了一种电流模式逻辑数字电路，包括具有至少一个数据输入节点和至少一个输出节点的逻辑电路组件。负载耦合在电源节点和输出节点之间。负载包括耦合到输出节点的折叠有源电感器。

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