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1. 发明授权

US09002155B2 Integrated optical-electronic interface in programmable integrated circuit device 有权
标题翻译：集成光电子接口可编程集成电路器件
公开(公告)号：US09002155B2
公开(公告)日：2015-04-07
申请号：US13360314
申请日：2012-01-27
申请人： Peng Li , Sergey Shumarayev , Jon M. Long , Tien Duc Pham
发明人： Peng Li , Sergey Shumarayev , Jon M. Long , Tien Duc Pham
IPC分类号： G02B6/42 , G02B6/43 , G02B6/12 , H04J14/02 , H04B10/40
CPC分类号： H04J14/02 , G02B6/12 , G02B6/4249 , G02B6/4257 , G02B6/4292 , G02B6/43 , H04B10/40
摘要： Systems that provide integrated circuit device circuitry having an integrated optical-electronic interface for high-speed off-device communications are provided. An optical-electronic interface may be incorporated into an integrated circuit device, freeing up some or all of the electrical I/O pins of the integrated circuit device. Transceiver I/O channels may be provided on an integrated circuit device that can be switched between electrical and optical transceiver I/O channels.
摘要翻译：提供了提供具有用于高速关闭设备通信的集成光电子接口的集成电路设备电路的系统。光电子接口可并入集成电路器件中，释放集成电路器件的部分或全部电I / O引脚。收发器I / O通道可以设置在可以在电和光收发器I / O通道之间切换的集成电路装置上。

2. 发明申请

US20120251116A1 INTEGRATED OPTICAL-ELECTRONIC INTERFACE IN PROGRAMMABLE INTEGRATED CIRCUIT DEVICE 有权
标题翻译：可编程集成电路设备中的集成光电接口
公开(公告)号：US20120251116A1
公开(公告)日：2012-10-04
申请号：US13360314
申请日：2012-01-27
申请人： Peng Li , Sergey Shumarayev , Jon M. Long , Tien Duc Pham
发明人： Peng Li , Sergey Shumarayev , Jon M. Long , Tien Duc Pham
IPC分类号： H04J14/02 , H04B10/02 , H04B10/06
CPC分类号： H04J14/02 , G02B6/12 , G02B6/4249 , G02B6/4257 , G02B6/4292 , G02B6/43 , H04B10/40
摘要： Systems that provide integrated circuit device circuitry having an integrated optical-electronic interface for high-speed off-device communications are provided. An optical-electronic interface may be incorporated into an integrated circuit device, freeing up some or all of the electrical I/O pins of the integrated circuit device. Transceiver I/O channels may be provided on an integrated circuit device that can be switched between electrical and optical transceiver I/O channels.
摘要翻译：提供了提供具有用于高速关闭设备通信的集成光电子接口的集成电路设备电路的系统。光电子接口可并入集成电路器件中，释放集成电路器件的部分或全部电I / O引脚。收发器I / O通道可以设置在可以在电和光收发器I / O通道之间切换的集成电路装置上。

3. 发明授权

US08542042B1 Phase-locked loop architecture and clock distribution system 有权
标题翻译：锁相环架构和时钟分配系统
公开(公告)号：US08542042B1
公开(公告)日：2013-09-24
申请号：US13532528
申请日：2012-06-25
申请人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff
发明人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff
IPC分类号： H03L7/06
CPC分类号： H03L7/23 , G06F1/10 , H03L7/0807 , H03L7/183 , H03L7/197 , H03L7/1974 , H04L7/0331
摘要： One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种可断裂的PLL电路。断裂PLL电路包括产生第一频率输出的第一锁相环电路，第二锁相环电路; 布置成产生第二频率输出和多个共享输出资源。可重构电路被布置成使得第一和第二频率输出中的任一个可由多个共享输出资源中的每一个接收。另一实施例涉及一种集成电路，其包括多个PMA模块，多个多用途PLL电路和可编程时钟网络。可编程时钟网络被布置为允许由多用途PLL电路输出的时钟信号被PMA模块选择性地用于收发器应用或由用于非收发器应用的其它电路。还公开了其它实施例和特征。

4. 发明授权

US08619931B1 Multi-purpose phase-locked loop for low cost transceiver 有权
标题翻译：用于低成本收发器的多功能锁相环
公开(公告)号：US08619931B1
公开(公告)日：2013-12-31
申请号：US12622152
申请日：2009-11-19
申请人： Tien Duc Pham , Sergey Shumarayev , Tim Tri Hoang , Thungoc M. Tran , Vinh Van Ho , Leon Zheng
发明人： Tien Duc Pham , Sergey Shumarayev , Tim Tri Hoang , Thungoc M. Tran , Vinh Van Ho , Leon Zheng
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H04L7/002
摘要： Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.
摘要翻译：提供了具有能够在没有专用锁相环电路的情况下能够进行高速（例如，1Gbps）操作的收发器的集成电路。一个这样的集成电路设备可以包括能够发送和接收大约1Gbps或更大的串行信号的一个或多个收发器，以及能够向一个或多个收发器提供多相时钟信号的多用途锁相环。

5. 发明授权

US08537956B1 Techniques for generating fractional periodic signals 有权
$Techniques for generating fractional periodic signals$
标题翻译：产生分数周期信号的技术
公开(公告)号：US08537956B1
公开(公告)日：2013-09-17
申请号：US12954514
申请日：2010-11-24
申请人： Tien Duc Pham , Leon Zheng , Sergey Shumarayev , Zhi Y. Wong , Paul B. Ekas
发明人： Tien Duc Pham , Leon Zheng , Sergey Shumarayev , Zhi Y. Wong , Paul B. Ekas
IPC分类号： H03D3/24
CPC分类号： H03L7/0802 , H03L7/1976 , H04J3/047 , H04J3/062
摘要： A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.
摘要翻译：解复用器电路将具有不同数据速率的输入数据分离成输出数据。锁相环电路产生具有基于第二时钟信号的频率的平均频率乘以分数非整数的第一时钟信号。串行器电路串行化一组输出数据以响应于由锁相环电路产生的第一时钟信号之一产生串行数据信号。

6. 发明授权

US08228102B1 Phase-locked loop architecture and clock distribution system 有权
标题翻译：锁相环架构和时钟分配系统
公开(公告)号：US08228102B1
公开(公告)日：2012-07-24
申请号：US12717062
申请日：2010-03-03
申请人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
发明人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
IPC分类号： H03L7/06
CPC分类号： H03L7/23 , G06F1/10 , H03L7/0807 , H03L7/183 , H03L7/197 , H03L7/1974 , H04L7/0331
摘要： One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，该集成电路包括集成电路的第一侧上的第一条锁相环（PLL）电路，以及集成电路的第二侧的第二条PLL电路，该第二条与第一条侧。可以通过对集成电路进行编程来配置第一和第二条带中的PLL电路。另一实施例涉及包括多个锁相环（PLL）电路和与多个PLL电路相邻的多个物理介质连接（PMA）三元组模块的集成电路。每个PMA三元组模块包括第一，第二和第三通道。第一和第三通道被布置为用作接收通道，并且第二通道被布置为可配置为接收通道或时钟倍增单元。还公开了其它实施例和特征。

7. 发明授权

US08744012B1 On-chip eye viewer architecture for highspeed transceivers 有权
标题翻译：用于高速收发器的片上眼睛查看器架构
公开(公告)号：US08744012B1
公开(公告)日：2014-06-03
申请号：US13369108
申请日：2012-02-08
申请人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
发明人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
IPC分类号： H03K9/00
CPC分类号： H04L1/203 , G01R31/31711
摘要： System, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with a serial input signal either during or after equalization. The device may include an equalizer and eye viewer circuitry configured to select a node of the equalizer for eye monitoring of the input signal, which may be during or after equalization. In one embodiment, the eye viewer circuitry may provide a separate sampler for each respective node, while sharing a control logic and phase interpolator among the samplers. The eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the serial input signal, as seen from the selected node of the equalizer.
摘要翻译：提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和设备。例如，集成电路器件的一个实施例可能能够在均衡期间或之后确定与串行输入信号相关联的眼图。该装置可以包括均衡器和眼睛观察器电路，其被配置为选择均衡器的节点，用于在均衡期间或之后的输入信号的眼睛监视。在一个实施例中，眼睛观察器电路可以为每个相应节点提供单独的采样器，同时在采样器之间共享控制逻辑和相位插值器。从均衡器的选定节点看，眼睛观察器电路可以确定与串行输入信号相关联的眼图的水平和垂直边界。

8. 发明授权

US08626474B2 Simulation tool for high-speed communications links 有权
标题翻译：用于高速通信链接的仿真工具
公开(公告)号：US08626474B2
公开(公告)日：2014-01-07
申请号：US12762848
申请日：2010-04-19
申请人： Peng Li , Masashi Shimanouchi , Thungoc M. Tran , Sergey Shumarayev
发明人： Peng Li , Masashi Shimanouchi , Thungoc M. Tran , Sergey Shumarayev
IPC分类号： G06F7/60 , G06G7/62 , G06F17/50
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/10
摘要： A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.
摘要翻译：提供了一种用于模拟高速通信链路系统的链路仿真工具。通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。链接仿真工具可以使用行为模型对每个子系统进行建模。行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎的链接系统。链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

9. 发明授权

US08504882B2 Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations 有权
标题翻译：用于执行或促进示波器，抖动和/或误码率测试仪操作的集成电路的电路
公开(公告)号：US08504882B2
公开(公告)日：2013-08-06
申请号：US12884305
申请日：2010-09-17
申请人： Peng Li , Masashi Shimanouchi , Sergey Shumarayev , Weiqi Ding , Siriram Narayan , Daniel Tun Lai Chow , Mingde Pan
发明人： Peng Li , Masashi Shimanouchi , Sergey Shumarayev , Weiqi Ding , Siriram Narayan , Daniel Tun Lai Chow , Mingde Pan
IPC分类号： G06F11/00
CPC分类号： G06F11/267
摘要： An integrated circuit (“IC”) includes circuitry for use in testing a serial data signal. One such IC includes circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. One such IC also includes circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. Such an IC provides output signals indicative of results of its operations. One such IC operates in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.
摘要翻译：集成电路（“IC”）包括用于测试串行数据信号的电路。一个这样的IC包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。一个这样的IC还包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。这样的IC提供指示其操作结果的输出信号。一个这样的IC以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。

10. 发明申请

US20120072785A1 BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER 有权
标题翻译：从眼睛观察器接收串行数据信号的位错误率检查器
公开(公告)号：US20120072785A1
公开(公告)日：2012-03-22
申请号：US12884923
申请日：2010-09-17
申请人： Weiqi Ding , Mingde Pan , Peng Li , Sergey Shumarayev , Masashi Shimanouchi
发明人： Weiqi Ding , Mingde Pan , Peng Li , Sergey Shumarayev , Masashi Shimanouchi
IPC分类号： G06F11/00
CPC分类号： H04L1/203 , G01R31/3171
摘要： An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.
摘要翻译：提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。在一个实现中，BER检查器是专用的BER检查器。在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

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