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1. 发明授权

US08619931B1 Multi-purpose phase-locked loop for low cost transceiver 有权
标题翻译：用于低成本收发器的多功能锁相环
公开(公告)号：US08619931B1
公开(公告)日：2013-12-31
申请号：US12622152
申请日：2009-11-19
申请人： Tien Duc Pham , Sergey Shumarayev , Tim Tri Hoang , Thungoc M. Tran , Vinh Van Ho , Leon Zheng
发明人： Tien Duc Pham , Sergey Shumarayev , Tim Tri Hoang , Thungoc M. Tran , Vinh Van Ho , Leon Zheng
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H04L7/002
摘要： Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.
摘要翻译：提供了具有能够在没有专用锁相环电路的情况下能够进行高速（例如，1Gbps）操作的收发器的集成电路。一个这样的集成电路设备可以包括能够发送和接收大约1Gbps或更大的串行信号的一个或多个收发器，以及能够向一个或多个收发器提供多相时钟信号的多用途锁相环。

2. 发明授权

US08294500B1 Multi-phase interpolators and related methods 有权
标题翻译：多相内插器及相关方法
公开(公告)号：US08294500B1
公开(公告)日：2012-10-23
申请号：US12621493
申请日：2009-11-18
申请人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang , Van Ton-That
发明人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang , Van Ton-That
IPC分类号： H03H11/16
CPC分类号： G06G7/30
摘要： A phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.
摘要翻译：相位插值器电路包括耦合以形成差分对的第一和第二晶体管，负载电路，第一组开关电路，第二组开关电路和电流源。第一组开关电路耦合在第一晶体管和负载电路之间。第二组开关电路耦合在第二晶体管和负载电路之间。电流源为差分对提供电流。

3. 发明授权

US07994837B1 Techniques for phase interpolation 有权
标题翻译：相位插值技术
公开(公告)号：US07994837B1
公开(公告)日：2011-08-09
申请号：US12537634
申请日：2009-08-07
申请人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang
发明人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang
IPC分类号： H03H11/16
CPC分类号： H03H11/22
摘要： A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between the second transistor and the second load circuit, a current source circuit, and a third switch circuit coupled between the differential pair and the current source circuit. A phase interpolator circuit can include three differential pairs of transistors. Six periodic input signals having six different phases are concurrently provided to control inputs of transistors in the three differential pairs of transistors. The phase interpolator circuit generates a selected phase in an output signal in response to four of the periodic input signals.
摘要翻译：相位插值器电路可以包括耦合以形成差分对的第一和第二晶体管，第一和第二负载电路，耦合在第一晶体管和第一负载电路之间的第一开关电路，耦合在第二晶体管和第二负载电路之间的第二开关电路负载电路，电流源电路和耦合在差分对和电流源电路之间的第三开关电路。相位内插器电路可以包括三个差分对的晶体管。具有六个不同相位的六个周期性输入信号被同时提供以控制三个差分对晶体管中的晶体管的输入。相位插值器电路响应于四个周期性输入信号而在输出信号中产生所选择的相位。

4. 发明授权

US08049532B1 Level shifter circuit with a thin gate oxide transistor 有权
标题翻译：具有薄栅极氧化物晶体管的电平移位电路
公开(公告)号：US08049532B1
公开(公告)日：2011-11-01
申请号：US12823596
申请日：2010-06-25
申请人： Simardeep Maangat , Vinh Van Ho , Tim Tri Hoang
发明人： Simardeep Maangat , Vinh Van Ho , Tim Tri Hoang
IPC分类号： H03K19/0175 , H03L5/00
CPC分类号： H03L7/085 , H03K19/017509 , H03L7/087
摘要： A level shifting circuit with a thin gate transistor connected to the input of the output stage is presented. The level shifting circuit has an input stage that receives an input that is at first voltage. A transistor with a thin gate oxide has one terminal connected to the input stage and another terminal coupled to an input of the output stage. The output stage of the level shifting circuit is implemented with thick gate oxide transistors.
摘要翻译：提出了一种具有连接到输出级的输入端的薄栅极晶体管的电平移动电路。电平移位电路具有接收处于第一电压的输入的输入级。具有薄栅极氧化物的晶体管具有连接到输入级的一个端子和耦合到输出级的输入的另一个端子。电平移位电路的输出级由厚栅极氧化物晶体管实现。

5. 发明授权

US07893726B1 Leakage compensation and improved setup/hold time in a dynamic flip-flop 有权
标题翻译：在动态触发器中泄漏补偿和改进的设置/保持时间
公开(公告)号：US07893726B1
公开(公告)日：2011-02-22
申请号：US11782443
申请日：2007-07-24
申请人： Vinh Van Ho , Tim Tri Hoang
发明人： Vinh Van Ho , Tim Tri Hoang
IPC分类号： G01R19/00
CPC分类号： G11C7/065 , G11C11/412 , H03K3/012 , H03K3/356139
摘要： A dynamic flip-flop includes first and second input stages forming a differential input stage adapted to receive differential data. The flip-flop is reset in response to a reset signal. To ensure proper operation, a transistor disposed between the first and second input stages is always maintained active to provide a conduction path between the ground terminal and the nodes that may be charged from the supply voltage. To improve the setup and hold time of the flip-flop, the clock signal is applied to a first transistor disposed in the first input stage and a second transistor disposed in the second input stage.
摘要翻译：动态触发器包括形成适于接收差分数据的差分输入级的第一和第二输入级。触发器响应于复位信号被复位。为了确保正常操作，设置在第一和第二输入级之间的晶体管总是保持有效，以在接地端子和节点之间提供可以从电源电压充电的导电路径。为了改善触发器的设置和保持时间，时钟信号被施加到设置在第一输入级中的第一晶体管和设置在第二输入级中的第二晶体管。

6. 发明授权

US07521964B1 High-speed level-shifting circuit 失效
标题翻译：高速电平转换电路
公开(公告)号：US07521964B1
公开(公告)日：2009-04-21
申请号：US11691106
申请日：2007-03-26
申请人： Mei Luo , Vinh Van Ho
发明人： Mei Luo , Vinh Van Ho
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528 , H03K19/01707
摘要： In level-shifting circuitry for shifting low-voltage-domain signals to a high-voltage domain, one of two output transistors is driven with one of the low-voltage-domain signals, thereby reducing loading on the output and increasing output speed and bandwidth. The circuitry can be mirrored for differential operation. When included in a serial interface of a programmable logic device, the circuitry can be programmably selectable between single-ended and differential operation.
摘要翻译：在用于将低电压域信号移位到高电压域的电平移位电路中，两个输出晶体管中的一个由低电压域信号中的一个驱动，从而减少输出上的负载并增加输出速度和带宽。电路可以镜像差分操作。当包括在可编程逻辑器件的串行接口中时，电路可以在单端和差分工作之间进行可编程选择。

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