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1. 发明授权

US08537956B1 Techniques for generating fractional periodic signals 有权
$Techniques for generating fractional periodic signals$
标题翻译：产生分数周期信号的技术
公开(公告)号：US08537956B1
公开(公告)日：2013-09-17
申请号：US12954514
申请日：2010-11-24
申请人： Tien Duc Pham , Leon Zheng , Sergey Shumarayev , Zhi Y. Wong , Paul B. Ekas
发明人： Tien Duc Pham , Leon Zheng , Sergey Shumarayev , Zhi Y. Wong , Paul B. Ekas
IPC分类号： H03D3/24
CPC分类号： H03L7/0802 , H03L7/1976 , H04J3/047 , H04J3/062
摘要： A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.
摘要翻译：解复用器电路将具有不同数据速率的输入数据分离成输出数据。锁相环电路产生具有基于第二时钟信号的频率的平均频率乘以分数非整数的第一时钟信号。串行器电路串行化一组输出数据以响应于由锁相环电路产生的第一时钟信号之一产生串行数据信号。

2. 发明授权

US08327154B1 Apparatus and a method to configure a programmable device 有权
标题翻译：用于配置可编程设备的装置和方法
公开(公告)号：US08327154B1
公开(公告)日：2012-12-04
申请号：US13097918
申请日：2011-04-29
申请人： Dirk A. Reese , Paul B. Ekas
发明人： Dirk A. Reese , Paul B. Ekas
IPC分类号： G06F11/30 , H03K19/177
CPC分类号： G06F21/572 , G06F21/76 , G06F2221/0704 , G06F2221/0706 , H03K19/17768
摘要： A method to configure a programmable device is disclosed. The method includes receiving a scrambled configuration data at the programmable device. A bit sequence of a device tag that is stored in the programmable device is verified by determining whether the bit sequence of the device tag stored in the programmable device matches a bit sequence of a device tag within the scrambled configuration data. If the bit sequences match, the scrambled configuration data is transferred to a data re-formatter for descrambling. The descrambled configuration data is then transferred to a configuration memory of the programmable device. Circuitry that enables the method is also disclosed.
摘要翻译：公开了一种配置可编程设备的方法。该方法包括在可编程设备处接收加扰的配置数据。存储在可编程设备中的设备标签的位序列通过确定存储在可编程设备中的设备标签的位序列是否与加扰配置数据内的设备标签的位序列匹配来验证。如果比特序列匹配，则将加扰的配置数据传送到数据重新格式化器以进行解扰。然后将解扰的配置数据传送到可编程设备的配置存储器。还公开了实现该方法的电路。

3. 发明授权

US08892793B1 Techniques for oversampling a data stream in an integrated circuit 有权
标题翻译：在集成电路中过采样数据流的技术
公开(公告)号：US08892793B1
公开(公告)日：2014-11-18
申请号：US13279145
申请日：2011-10-21
申请人： Zhi Y. Wong , Albert Lee , Keen Yew Loke , Kia Leong Tan , Paul B. Ekas , Siew Leong Lam
发明人： Zhi Y. Wong , Albert Lee , Keen Yew Loke , Kia Leong Tan , Paul B. Ekas , Siew Leong Lam
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F5/06
摘要： Techniques for sampling input data streams with an integrated circuit (IC) are provided. The technique includes receiving a first input stream at a first operating rate. The first input stream is transmitted to a plurality of subsequent transceiver channels on the IC. The first input stream is then sampled at a second operating rate at each of the plurality of subsequent transceiver channels with each of the plurality of subsequent transceiver channels outputting a data stream at the second operating rate. The data stream from each of the plurality of subsequent transceiver channels is adjusted. A data stream from one of the plurality of subsequent transceiver channels is selected as an output of the IC.
摘要翻译：提供了使用集成电路（IC）对输入数据流进行采样的技术。该技术包括以第一工作速率接收第一输入流。第一输入流被发送到IC上的多个后续收发器通道。然后，以多个后续收发器通道中的每一个以第二工作速率对第一输入流进行采样，其中多个后续收发器通道中的每一个以第二操作速率输出数据流。调整来自多个后续收发器通道中的每一个的数据流。选择来自多个后续收发器通道之一的数据流作为IC的输出。

4. 发明申请

US20120221919A1 ERROR DETECTION AND CORRECTION CIRCUITRY 有权
标题翻译：错误检测和校正电路
公开(公告)号：US20120221919A1
公开(公告)日：2012-08-30
申请号：US13035826
申请日：2011-02-25
申请人： Paul B. Ekas , David Lewis
发明人： Paul B. Ekas , David Lewis
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G06F11/1076 , G06F11/10 , G06F11/1048 , G11C11/412 , G11C29/52 , G11C2029/0411 , H03K19/17768
摘要： Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.
摘要翻译：具有存储器电路的集成电路可以包括错误检测电路和纠错电路。误差检测电路可用于检测存储器电路中的软错误。错误检测电路可以包括用于执行奇偶校验的逻辑门。错误检测电路可以具有交织结构以提供交错数据位处理，可以具有减少逻辑门延迟的树结构，并且可以被流水线化以优化性能。存储器电路可以与交错结构一起加载交错奇偶校验位以提供多位错误检测能力。奇偶校验位可以使用设计工具预先计算或在设备配置期间计算。响应于存储器错误的检测，错误校正电路可用于扫描存储器电路的期望部分并校正存储器错误。

5. 发明授权

US08984367B2 Error detection and correction circuitry 有权
标题翻译：错误检测和校正电路
公开(公告)号：US08984367B2
公开(公告)日：2015-03-17
申请号：US13035826
申请日：2011-02-25
申请人： Paul B. Ekas , David Lewis
发明人： Paul B. Ekas , David Lewis
IPC分类号： G11C29/00 , G11C29/52 , G06F11/10 , H03K19/177 , G11C11/412 , G11C29/04
CPC分类号： G06F11/1076 , G06F11/10 , G06F11/1048 , G11C11/412 , G11C29/52 , G11C2029/0411 , H03K19/17768
摘要： Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.
摘要翻译：具有存储器电路的集成电路可以包括错误检测电路和纠错电路。误差检测电路可用于检测存储器电路中的软错误。错误检测电路可以包括用于执行奇偶校验的逻辑门。错误检测电路可以具有交织结构以提供交错数据位处理，可以具有减少逻辑门延迟的树结构，并且可以被流水线化以优化性能。存储器电路可以与交错结构一起加载交错奇偶校验位以提供多位错误检测能力。奇偶校验位可以使用设计工具预先计算或在设备配置期间计算。响应于存储器错误的检测，错误校正电路可用于扫描存储器电路的期望部分并校正存储器错误。

6. 发明授权

US5350953A Digitally weighted neuron for artificial neural network 失效
标题翻译：人工神经网络的数字加权神经元
公开(公告)号：US5350953A
公开(公告)日：1994-09-27
申请号：US69943
申请日：1993-05-28
申请人： Richard M. Swenson , John C. Cole, III , Steve L. Holmes , Paul B. Ekas
发明人： Richard M. Swenson , John C. Cole, III , Steve L. Holmes , Paul B. Ekas
IPC分类号： G06N3/063 , H03K19/23 , H03K19/08
CPC分类号： G06N3/063
摘要： A neuron for an artificial neural network provides digital weighting of input signals at a common portion of the neuron rather than at each synapse. The neuron is adapted for use of differential signals, and the weighting may be provided by field effect transistors of different widths, by subtracting a plurality of differential signal components from an opposite most significant component, or by subtracting one half of a differential signal component from the opposite next most significant component. The neuron may provide binary sign selection and digit selection by switching input and reference signals at each synapse.
摘要翻译：用于人造神经网络的神经元在神经元的公共部分而不是在每个突触处提供输入信号的数字加权。该神经元适于使用差分信号，并且可以通过从相对最高有效分量减去多个差分信号分量或者从相对最高有效分量中减去一半的差分信号分量来提供来自不同宽度的场效应晶体管的加权，相反的下一个最重要的组件。神经元可以通过在每个突触处切换输入和参考信号来提供二进制符号选择和数字选择。

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