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1. 发明申请

US20130056837A1 SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE 有权
标题翻译：用于高K金属栅极设备的自对准绝缘膜
公开(公告)号：US20130056837A1
公开(公告)日：2013-03-07
申请号：US13244365
申请日：2011-09-24
申请人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
发明人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
摘要翻译：制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。在半导体衬底上形成金属栅极结构，并在其上形成一个薄的电介质膜。薄介电膜包括从金属栅极与金属组合的氮氧化合物。该方法还包括在金属栅极结构的两侧提供层间电介质（ILD）。

2. 发明申请

US20070178693A1 INTERLAYER INTERCONNECT OF THREE-DIMENSIONAL MEMORY AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：三维存储器的层间互连及其制造方法
公开(公告)号：US20070178693A1
公开(公告)日：2007-08-02
申请号：US11423619
申请日：2006-06-12
申请人： Pei-Ren Jeng
发明人： Pei-Ren Jeng
IPC分类号： H01L21/44
CPC分类号： H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/085
摘要： An interlayer interconnect structure of a three-dimensional memory includes memory cell groups, each composed of a plurality of memory cells and connected to their respective selection transistors, because of special arrangement of lines and first plugs as well as line layouts. The line layouts involve disposing a plurality of lines on each of a plurality of horizontal levels, and selectively forming second plugs between adjoining lines disposed on upper and lower horizontal levels, such that the plugs selectively connect the adjoining upper and lower lines to each other. Since identical layout patterns are adopted in individual stacking states of stacking layers disposed in the three-dimensional memory, the upper lines and the lower lines of the stacking layers of the three-dimensional memory share the same layouts, leading to a reduction in the number of masks used, simpler process adjustment, and lower costs.
摘要翻译：三维存储器的层间互连结构包括存储单元组，每个存储单元组由多个存储单元组成，并且由于线和第一插头的特殊布置以及线路布局而连接到它们各自的选择晶体管。线路布局涉及在多个水平平面中的每一个上布置多个线，并且在布置在上部和下部水平水平的相邻线之间选择性地形成第二插塞，使得插头选择性地将相邻的上部和下部线路相互连接。由于在设置在三维存储器中的堆叠层的各个堆叠状态中采用相同的布局图案，所以三维存储器的堆叠层的上层和下层共享相同的布局，导致数量的减少使用的面罩，更简单的工艺调整和更低的成本。

3. 发明申请

US20070105316A1 Nanocrystal memory element, method for fabricating the same and memory having the memory element 审中-公开
标题翻译：纳米晶体存储元件，其制造方法和具有存储元件的存储器
公开(公告)号：US20070105316A1
公开(公告)日：2007-05-10
申请号：US11495528
申请日：2006-07-31
申请人： Pei-Ren Jeng
发明人： Pei-Ren Jeng
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , B82Y10/00 , H01L29/40114 , H01L29/42332
摘要： A nanocrystal memory element and a method for fabricating the same involves repeatedly and alternately depositing, by atomic layer deposition, conductive layers and dielectric layers on a substrate with a tunnel oxide layer formed thereon, forming multiple layers of nanocrystal groups as a result of crystallization of conductive layers in a rapid thermal annealing process, and forming a gate on the top dielectric layer. The nanocrystal groups disposed at any two neighboring levels are separated by one dielectric layer, thus a plurality of nanocrystals formed in an integration layer are disposed at the same level. Barrier widths between a channel and the nanocrystals of the nanocrystal groups disposed at the same level are equal. Therefore, the nanocrystals at the same level are subjected the same electric field when voltage is applied to the gate, resulting in improved transistor performance, enhanced control of threshold voltage, and avoidance of over-erasing.
摘要翻译：纳米晶体存储元件及其制造方法涉及通过原子层沉积，在其上形成有隧道氧化物层的衬底上的导电层和电介质层反复交替沉积，形成多层纳米晶体基团作为结晶的结果导电层，并且在顶部介电层上形成栅极。设置在任何两个相邻级别的纳米晶体组由一个电介质层分离，因此在积分层中形成的多个纳米晶体设置在相同的水平。通道与布置在同一水平的纳米晶体的纳米晶体之间的阻挡宽度相等。因此，当对栅极施加电压时，相同电平的纳米晶体受到相同的电场，从而提高了晶体管性能，增强了阈值电压的控制，并避免了过度擦除。

4. 发明申请

US20060172490A1 Method of improving flash memory performance 有权
公开(公告)号：US20060172490A1
公开(公告)日：2006-08-03
申请号：US11049230
申请日：2005-02-02
申请人： Pei-Ren Jeng , Hsuan-Ling Kao
发明人： Pei-Ren Jeng , Hsuan-Ling Kao
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/66825
摘要： A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure, for forming side wall spacers; next, performing a first anneal on the substrate and the enclosed gate structure; then, performing a cell reoxidation on the substrate and the enclosed gate structure by dilute oxidation process using mixed gas comprising oxygen O2 and nitrogen N2. The invention reduces encroachment issues in the interpoly dielectric layer and the tunnel oxide and improves gate coupling ratio (GCR).

5. 发明授权

US06939768B2 Method of forming self-aligned contacts 有权
标题翻译：形成自对准触点的方法
公开(公告)号：US06939768B2
公开(公告)日：2005-09-06
申请号：US10403060
申请日：2003-04-01
申请人： Pei-Ren Jeng
发明人： Pei-Ren Jeng
IPC分类号： H01L21/28 , H01L21/60 , H01L21/336 , H01L21/331 , H01L21/338 , H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28247
摘要： A method of forming self-aligned contacts that includes providing at least one stacked-gate structure on a semiconductor substrate, forming a first dielectric layer on the stacked-gate structure and the semiconductor substrate, forming a second dielectric layer on the first dielectric layer, the second dielectric layer being etch selective relative to the first dielectric layer, etching the second dielectric layer to expose a portion of the first dielectric layer formed on a top surface and along at least a portion of upper sidewalls of the stacked-gate structure, removing the exposed portion of the first dielectric layer, and forming a third dielectric layer on the sidewalls of the stacked-gate structure.
摘要翻译：一种形成自对准触点的方法，包括在半导体衬底上提供至少一个堆叠栅极结构，在堆叠栅极结构和半导体衬底上形成第一电介质层，在第一介电层上形成第二电介质层，所述第二电介质层相对于所述第一电介质层具有蚀刻选择性，蚀刻所述第二电介质层以暴露形成在所述第一电介质层的顶表面上并沿着所述堆叠栅极结构的上侧壁的至少一部分的部分，第一电介质层的暴露部分，并且在堆叠栅极结构的侧壁上形成第三电介质层。

6. 发明授权

US06521548B2 Method of forming a spin-on-passivation layer 有权
公开(公告)号：US06521548B2
公开(公告)日：2003-02-18
申请号：US09878361
申请日：2001-06-12
申请人： Pei-Ren Jeng
发明人： Pei-Ren Jeng
IPC分类号： H01L2131
CPC分类号： H01L21/02282 , H01L21/02118 , H01L21/0212 , H01L21/02274 , H01L21/312 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/76837
摘要： At least two neighboring metal lines are formed on a semiconductor substrate first, followed by the formation of a PE oxide layer on the semiconductor substrate, that uniformly covers the surface of the two neighboring metal lines and the gap between the two neighboring metal lines. A SOD layer on the PE oxide layer is created to fill the gap. Then the semiconductor substrate is directly heated by utilizing at least one hot plate fixed at a first predetermined temperature so as to expel the solvent out of the SOD layer. Finally, the semiconductor wafer is directly heated by utilizing a second hot plate fixed at a second predetermined temperature so as to cure the SOD layer for a predetermined time.

7. 发明授权

US06335274B1 Method for forming a high-RI oxide film to reduce fluorine diffusion in HDP FSG process 有权
标题翻译：用于形成高RI氧化膜以减少HDP FSG工艺中的氟扩散的方法
公开(公告)号：US06335274B1
公开(公告)日：2002-01-01
申请号：US09714128
申请日：2000-11-17
申请人： Shu-Li Wu , Pei-Ren Jeng
发明人： Shu-Li Wu , Pei-Ren Jeng
IPC分类号： H01L214763
CPC分类号： H01L21/02131 , H01L21/02304 , H01L21/31612 , H01L21/31629 , H01L21/76834
摘要： A method for forming a high-RI dielectric liner layer to prevent out diffusion of fluorine substances in an intermetal dielectric (IMD) layer of an semiconductor device is provided. The method comprises following steps. First, a patterned conductive layer is deposited on a substrate. Then, a dielectric liner layer is formed by high density plasma enhanced chemical vapor deposition method or plasma enhanced chemical vapor deposition method. The dielectric liner layer is silicon dioxide and has a high-RI between about 1.5 to 1.8. Next, a fluorinated silicate glass layer is deposited on the dielectric liner layer. The high-RI dielectric liner layer is used to reduce out diffusion of fluorine substances in the fluorinated silicate glass layer. Last, it is proceeded a chemical mechanism polishing process to remove additional fluorinated silicate glass layer and the dielectric liner layer.
摘要翻译：提供了形成高RI电介质衬垫层以防止氟物质在半导体器件的金属间电介质（IMD）层中的扩散的方法。该方法包括以下步骤。首先，将图案化的导电层沉积在衬底上。然后，通过高密度等离子体增强化学气相沉积法或等离子体增强化学气相沉积法形成电介质衬垫层。电介质衬垫层是二氧化硅，并且具有在约1.5至1.8之间的高RI。接下来，氟化硅酸盐玻璃层沉积在电介质衬垫层上。高RI介电衬垫层用于减少氟化硅酸盐玻璃层中氟物质的扩散。最后，进行化学机构抛光工艺以除去附加的氟化硅酸盐玻璃层和介电衬里层。

8. 发明授权

US5877074A Method for improving the electrical property of gate in polycide structure 失效
标题翻译：改善多晶硅结构栅极电性能的方法
公开(公告)号：US5877074A
公开(公告)日：1999-03-02
申请号：US998958
申请日：1997-12-29
申请人： Pei-Ren Jeng , Chun-Cho Chen
发明人： Pei-Ren Jeng , Chun-Cho Chen
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28061
摘要： A method for improving the electrical property of gate in polycide structure is disclosed. First, a gate oxide layer is formed on the surface of the silicon substrate. The following procedure acts as one of the key points for the invention comprising the process steps of (1) forming a highly-doped polysilicon layer on the gate oxide, (2) forming an undoped amorphous silicon layer on the polysilicon layer, and followed by (3) forming a tungsten silicon layer on the amorphous silicon. Next, annealing at high temperature and in short time is performed. Such a stacked gate structure has low resistance and can solve the following problems: (1)peeling of tungsten silicide after annealing, (2) degradation of the electrical property of gate due to the diffusing and penetration of fluorine atoms coming from tungsten silicide.
摘要翻译：公开了一种改善多晶硅结构中栅极电性能的方法。首先，在硅衬底的表面上形成栅氧化层。以下步骤用作本发明的关键点之一，其包括以下步骤：（1）在栅极氧化物上形成高度掺杂的多晶硅层，（2）在多晶硅层上形成未掺杂的非晶硅层，（3）在非晶硅上形成钨硅层。接下来，进行高温退火和短时间退火。这种堆叠栅极结构具有低电阻并且可以解决以下问题：（1）退火后硅化钨的剥离，（2）由于来自硅化钨的氟原子的扩散和渗透导致的栅极电性能的劣化。

9. 发明授权

US09337059B2 Apparatus and methods for annealing wafers 有权
标题翻译：用于退火晶圆的设备和方法
公开(公告)号：US09337059B2
公开(公告)日：2016-05-10
申请号：US13215909
申请日：2011-08-23
申请人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
发明人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
IPC分类号： H01L21/00 , H01L21/324 , H01L21/268 , H01L21/20 , H01L21/36 , H01L21/44
CPC分类号： H01L21/67115 , B23K26/352 , H01L21/2636 , H01L21/268 , H01L21/324
摘要： A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
摘要翻译：一种方法包括在晶片上进行退火。晶片包括晶片边缘区域和由晶片边缘区域包围的内部区域。在退火期间，施加在晶片边缘区域的一部分上的第一功率至少低于用于退火内部区域的第二功率。

10. 发明申请

US20130122676A1 SOURCE/DRAIN DOPING METHOD IN 3D DEVICES 有权
标题翻译： 3D设备中的源/排水方法
公开(公告)号：US20130122676A1
公开(公告)日：2013-05-16
申请号：US13293679
申请日：2011-11-10
申请人： Pei-Ren Jeng
发明人： Pei-Ren Jeng
IPC分类号： H01L21/225 , H01L21/336
CPC分类号： H01L21/823431 , H01L21/2255 , H01L21/823821 , H01L21/845 , H01L29/0847 , H01L29/66636 , H01L29/66803 , H01L29/7834
摘要： The present disclosure provides methods of semiconductor device fabrication for 3D devices. One method includes provide a substrate having a recess and forming a doping layer on the substrate and in the recess. The substrate is then annealed. The annealing drives dopants of a first type from the doping layer into the substrate. This can form a doped region that may be the source/drain extension of the 3D device. An epitaxial region is then grown in the recess. The epitaxial region can form the source/drain region of the 3D device.
摘要翻译：本公开提供了用于3D设备的半导体器件制造的方法。一种方法包括提供具有凹陷并在衬底上和凹部中形成掺杂层的衬底。然后将衬底退火。退火将掺杂层中的第一类掺杂剂驱动到衬底中。这可以形成可以是3D器件的源/漏扩展的掺杂区域。然后在凹槽中生长外延区域。外延区域可以形成3D器件的源极/漏极区域。

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