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1. 发明授权

US07091890B1 Multi-purpose source synchronous interface circuitry 有权
标题翻译：多用途源同步接口电路
公开(公告)号：US07091890B1
公开(公告)日：2006-08-15
申请号：US10919901
申请日：2004-08-17
申请人： Paul T. Sasaki , Jason R. Bergendahl , Atul Ghia , Hassan Bazargan , Ketan Sodha , Jian Tan , Qi Zhang , Suresh Menon
发明人： Paul T. Sasaki , Jason R. Bergendahl , Atul Ghia , Hassan Bazargan , Ketan Sodha , Jian Tan , Qi Zhang , Suresh Menon
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H04L7/0008
摘要： A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.
摘要翻译：描述了在集成电路的可配置逻辑中实例化的串行器 - 解串器。串行器 - 解串器包括输入解串器和输出串行器，其可以通过输入/输出板通常耦合。串行器和解串器中的每一个可以被配置为从单数据速率模式和双数据速率模式中选择的操作模式。串行器 - 解串器可以用作同步接口的一部分。

2. 发明授权

US07589557B1 Reversible input/output delay line for bidirectional input/output blocks 有权
标题翻译：用于双向输入/输出块的可逆输入/输出延迟线
公开(公告)号：US07589557B1
公开(公告)日：2009-09-15
申请号：US11405901
申请日：2006-04-18
申请人： Jason R. Bergendahl , Qi Zhang , Jian Tan , Matthew H. Klein
发明人： Jason R. Bergendahl , Qi Zhang , Jian Tan , Matthew H. Klein
IPC分类号： H03K19/173
CPC分类号： H03K5/159 , H03K19/017581 , H03K19/01759
摘要： An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e.g., by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.
摘要翻译：输入/输出（I / O）结构包括在用户设计中可用于输入路径，输出路径或输入和输出路径的延迟元件。在第一模式中，延迟元件包括在输入路径中。在第二模式中，延迟元件包括在输出路径中。在第三模式中，I / O结构包括输出信号路径和输入信号路径中的延迟，例如通过利用输出三态信号来控制延迟线的方向。当输出缓冲区正在驱动时，延迟被插入到输出路径中。当输出缓冲器被三态时，延迟被插入到输入路径中。因此，单个延迟元件由使用相同I / O焊盘的输入和输出信号动态共享。在可选的第四模式中，延迟元件被输入和输出信号旁路。

3. 发明授权

US08222954B1 Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device 有权
标题翻译：用于工艺，电压和温度变化的半导体器件的方法和装置
公开(公告)号：US08222954B1
公开(公告)日：2012-07-17
申请号：US12362412
申请日：2009-01-29
申请人： Guo Jun Ren , Qi Zhang , Ketan Sodha
发明人： Guo Jun Ren , Qi Zhang , Ketan Sodha
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K19/00369
摘要： A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.
摘要翻译：一种降低由于工艺，电压和温度（PVT）和/或其它变化原因导致的基于半导体的器件性能下降的方法和装置。使用自适应反馈机制来感测和纠正性能下降，同时促进诸如可编程逻辑器件（PLD）之类的集成电路（IC）内的可配置性。采用电压反馈机制来检测PVT变化，并自适应调整镜像电流参考以跟踪和基本上消除PVT变化。可以替代地使用多于一个的电压反馈机构来检测差分装置内的基于PVT的变化，由此利用第一电压反馈机构来检测共模电压变化，而第二电压反馈机构产生镜像参考电流基本上消除了共模电压变化，并促进了差动装置的对称运行。

4. 发明授权

US07728630B1 Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device 有权
标题翻译：用于工艺，电压和温度变化的半导体器件的方法和装置
公开(公告)号：US07728630B1
公开(公告)日：2010-06-01
申请号：US12362417
申请日：2009-01-29
申请人： Guo Jun Ren , Qi Zhang , Ketan Sodha
发明人： Guo Jun Ren , Qi Zhang , Ketan Sodha
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/00384 , H03K17/163 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device. Edge boosting modules are employed to improve performance during reduced output common mode voltage modes of operation.
摘要翻译：一种降低由于工艺，电压和温度（PVT）和/或其它变化原因导致的基于半导体的器件性能下降的方法和装置。使用自适应反馈机制来感测和纠正性能下降，同时促进诸如可编程逻辑器件（PLD）之类的集成电路（IC）内的可配置性。采用电压反馈机制来检测PVT变化，并自适应调整镜像电流参考以跟踪和基本上消除PVT变化。可以替代地使用多于一个的电压反馈机构来检测差分装置内的基于PVT的变化，由此利用第一电压反馈机构来检测共模电压变化，而第二电压反馈机构产生镜像参考电流基本上消除了共模电压变化，并促进了差动装置的对称运行。边缘升压模块用于在降低输出共模电压工作模式的同时提高性能。

5. 发明授权

US07551646B1 Data alignment and deskewing module 有权
标题翻译：数据对齐和脱斜模块
公开(公告)号：US07551646B1
公开(公告)日：2009-06-23
申请号：US10938151
申请日：2004-09-10
申请人： Qi Zhang , Jason R. Bergendahl , Atul V. Ghia , Suresh M. Menon
发明人： Qi Zhang , Jason R. Bergendahl , Atul V. Ghia , Suresh M. Menon
IPC分类号： H04J3/06
CPC分类号： H04J3/0629
摘要： A data alignment and deskewing module includes a delay calibration unit, a data alignment and deskew unit, and a delay unit. The delay calibration unit is operably coupled to generate a reference signal based on a reference clock and a mirrored delay line output signal. The data alignment and deskew unit is operably coupled to determine a delay selection signal based on a delayed and deskewed representation of an input data stream and propagation delay of a line on which the input data stream is received. The delay unit is operably coupled to produce the delayed and deskewed representation of the input data stream based on the reference signal and the delay selection signal.
摘要翻译：数据对准和去歪斜模块包括延迟校准单元，数据对准和去歪斜单元以及延迟单元。延迟校准单元可操作地耦合以基于参考时钟和镜像延迟线输出信号产生参考信号。数据对准和去歪斜单元可操作地耦合以基于输入数据流的延迟和偏斜校正表示以及接收输入数据流的线的传播延迟来确定延迟选择信号。延迟单元可操作地耦合以基于参考信号和延迟选择信号产生输入数据流的延迟和去歪斜表示。

6. 发明授权

US07456654B1 Method and apparatus for a programmable level translator 有权
标题翻译：用于可编程电平转换器的方法和装置
公开(公告)号：US07456654B1
公开(公告)日：2008-11-25
申请号：US11639995
申请日：2006-12-14
申请人： Prasad Rau , Venu M. Kondapalli , Jason R. Bergendahl , Qi Zhang
发明人： Prasad Rau , Venu M. Kondapalli , Jason R. Bergendahl , Qi Zhang
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528
摘要： A level translator includes a programmable booster stage that augments the drive level of the level translator under certain conditions. The booster stage is programmably activated. e.g., via a memory cell or control bit, and augments operation of the pull-up stages of a cross-coupled latch within the level translator. When the voltage levels at the high voltage portion of the level translator are reduced below a threshold voltage, the booster stage is activated to maintain proper operation of the level translator despite the reduced voltage levels.
摘要翻译：电平转换器包括一个可编程的增强器级，在某些条件下增加电平转换器的驱动电平。增强级可编程激活。例如经由存储器单元或控制位，并且增加电平转换器内的交叉耦合锁存器的上拉级的操作。当电平转换器的高电压部分的电压电平降低到阈值电压以下时，升压级被激活，以维持电平转换器的正常工作，尽管降低了电压电平。

7. 发明授权

US07480361B1 Phase lock detector 有权
标题翻译：锁相检测器
公开(公告)号：US07480361B1
公开(公告)日：2009-01-20
申请号：US10889553
申请日：2004-07-12
申请人： Qi Zhang , Atul Ghia
发明人： Qi Zhang , Atul Ghia
IPC分类号： H03D3/24
CPC分类号： H03L7/095 , H03L7/0812
摘要： Method and apparatus for phase lock detection is described. More particularly, a phase lock detection circuit (20) includes a synchronization circuit (23) coupled to receive a reference signal (31) and configured to provide a derivative signal (32). A phase lock detector (21) is coupled to receive the reference signal (31) and the derivative signal (32) and is configured to provide a cycle lock signal (24) indicating whether a phase lock exists within a lock window (57) for a clock cycle.
摘要翻译：描述用于锁相检测的方法和装置。更具体地，锁相检测电路（20）包括耦合以接收参考信号（31）并被配置为提供导数信号（32）的同步电路（23）。相位锁定检测器（21）被耦合以接收参考信号（31）和微分信号（32），并且被配置为提供循环锁定信号（24），其指示在锁定窗口（57）内是否存在相位锁定，用于一个时钟周期。

8. 发明授权

US07468615B1 Voltage level shifter 有权
标题翻译：电压电平转换器
公开(公告)号：US07468615B1
公开(公告)日：2008-12-23
申请号：US11729201
申请日：2007-03-28
申请人： Jian Tan , Qi Zhang
发明人： Jian Tan , Qi Zhang
IPC分类号： H03K19/094 , H03K19/0175 , H03L5/00
CPC分类号： H03K19/018528 , H03K19/00315
摘要： A high-speed, area-efficient level shifter includes transistors having a variety of oxide thicknesses. The level shifter has a protection circuit stage, and a current mirror stage that allows the level shifter to perform over a wide voltage range at a high frequency. The level shifter maintains rise time, fall time, and duty cycle over a wide range of input and output voltage levels.
摘要翻译：高速，面积有效的电平移位器包括具有各种氧化物厚度的晶体管。电平移位器具有保护电路级和允许电平移位器在高频下在宽电压范围内执行的电流镜级。电平转换器在宽范围的输入和输出电压电平下保持上升时间，下降时间和占空比。

9. 发明授权

US08058924B1 Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device 有权
标题翻译：用于工艺，电压和温度变化的半导体器件的方法和装置
公开(公告)号：US08058924B1
公开(公告)日：2011-11-15
申请号：US12361804
申请日：2009-01-29
申请人： Guo Jun Ren , Prasad Rau , Jian Tan , Qi Zhang
发明人： Guo Jun Ren , Prasad Rau , Jian Tan , Qi Zhang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K19/00384 , G11C29/022 , G11C29/028 , G11C2029/0409 , H03K19/018528
摘要： A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.
摘要翻译：一种降低由于工艺，电压和温度（PVT）和/或其它变化原因导致的基于半导体的器件性能下降的方法和装置。使用自适应反馈机制来感测和纠正性能下降，同时促进诸如可编程逻辑器件（PLD）之类的集成电路（IC）内的可配置性。采用电压反馈机制来检测PVT变化，并自适应调整镜像电流参考以跟踪和基本上消除PVT变化。可以替代地使用多于一个的电压反馈机构来检测差分装置内的基于PVT的变化，由此利用第一电压反馈机构来检测共模电压变化，而第二电压反馈机构产生镜像参考电流基本上消除了共模电压变化，并促进了差动装置的对称运行。

10. 发明授权

US07839173B1 High speed, low power signal level shifter 有权
标题翻译：高速，低功率信号电平转换器
公开(公告)号：US07839173B1
公开(公告)日：2010-11-23
申请号：US12539522
申请日：2009-08-11
申请人： Wenfeng Zhang , Qi Zhang , Jian Tan
发明人： Wenfeng Zhang , Qi Zhang , Jian Tan
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/01714
摘要： A system for signal level shifting in an IC can include a first inverter having a first pull-up device and a pull-down device, wherein the first inverter is operable to receive an input signal having a voltage potential at a logic high that does not disable the first pull-up device. The system can include a second inverter coupled in series to an output of the first inverter, and a control module coupled to the output of the first inverter and an output of the second inverter. Prior to the input signal transitioning to the logic high, the control module is operable to decouple the input signal from the first pull-up device, disable the first pull-up device, and close a feedback loop that latches an output state of the second inverter.
摘要翻译：用于IC中的信号电平移位的系统可以包括具有第一上拉装置和下拉装置的第一反相器，其中第一反相器可操作以接收具有不高于逻辑高的电压电位的输入信号禁用第一个上拉设备。该系统可以包括与第一反相器的输出串联耦合的第二反相器，以及耦合到第一反相器的输出和第二反相器的输出的控制模块。在输入信号转换到逻辑高电平之前，控制模块可操作以将输入信号与第一上拉装置去耦，禁用第一上拉装置，并闭合锁存第二上拉装置的输出状态的反馈环路逆变器。

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