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1. 发明授权

US08222954B1 Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device 有权
标题翻译：用于工艺，电压和温度变化的半导体器件的方法和装置
公开(公告)号：US08222954B1
公开(公告)日：2012-07-17
申请号：US12362412
申请日：2009-01-29
申请人： Guo Jun Ren , Qi Zhang , Ketan Sodha
发明人： Guo Jun Ren , Qi Zhang , Ketan Sodha
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K19/00369
摘要： A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.
摘要翻译：一种降低由于工艺，电压和温度（PVT）和/或其它变化原因导致的基于半导体的器件性能下降的方法和装置。使用自适应反馈机制来感测和纠正性能下降，同时促进诸如可编程逻辑器件（PLD）之类的集成电路（IC）内的可配置性。采用电压反馈机制来检测PVT变化，并自适应调整镜像电流参考以跟踪和基本上消除PVT变化。可以替代地使用多于一个的电压反馈机构来检测差分装置内的基于PVT的变化，由此利用第一电压反馈机构来检测共模电压变化，而第二电压反馈机构产生镜像参考电流基本上消除了共模电压变化，并促进了差动装置的对称运行。

2. 发明授权

US07728630B1 Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device 有权
标题翻译：用于工艺，电压和温度变化的半导体器件的方法和装置
公开(公告)号：US07728630B1
公开(公告)日：2010-06-01
申请号：US12362417
申请日：2009-01-29
申请人： Guo Jun Ren , Qi Zhang , Ketan Sodha
发明人： Guo Jun Ren , Qi Zhang , Ketan Sodha
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/00384 , H03K17/163 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device. Edge boosting modules are employed to improve performance during reduced output common mode voltage modes of operation.
摘要翻译：一种降低由于工艺，电压和温度（PVT）和/或其它变化原因导致的基于半导体的器件性能下降的方法和装置。使用自适应反馈机制来感测和纠正性能下降，同时促进诸如可编程逻辑器件（PLD）之类的集成电路（IC）内的可配置性。采用电压反馈机制来检测PVT变化，并自适应调整镜像电流参考以跟踪和基本上消除PVT变化。可以替代地使用多于一个的电压反馈机构来检测差分装置内的基于PVT的变化，由此利用第一电压反馈机构来检测共模电压变化，而第二电压反馈机构产生镜像参考电流基本上消除了共模电压变化，并促进了差动装置的对称运行。边缘升压模块用于在降低输出共模电压工作模式的同时提高性能。

3. 发明授权

US07091890B1 Multi-purpose source synchronous interface circuitry 有权
标题翻译：多用途源同步接口电路
公开(公告)号：US07091890B1
公开(公告)日：2006-08-15
申请号：US10919901
申请日：2004-08-17
申请人： Paul T. Sasaki , Jason R. Bergendahl , Atul Ghia , Hassan Bazargan , Ketan Sodha , Jian Tan , Qi Zhang , Suresh Menon
发明人： Paul T. Sasaki , Jason R. Bergendahl , Atul Ghia , Hassan Bazargan , Ketan Sodha , Jian Tan , Qi Zhang , Suresh Menon
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H04L7/0008
摘要： A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.
摘要翻译：描述了在集成电路的可配置逻辑中实例化的串行器 - 解串器。串行器 - 解串器包括输入解串器和输出串行器，其可以通过输入/输出板通常耦合。串行器和解串器中的每一个可以被配置为从单数据速率模式和双数据速率模式中选择的操作模式。串行器 - 解串器可以用作同步接口的一部分。

4. 发明授权

US07635990B1 Methods and apparatus for implementing an output circuit 有权
标题翻译：用于实现输出电路的方法和装置
公开(公告)号：US07635990B1
公开(公告)日：2009-12-22
申请号：US12175925
申请日：2008-07-18
申请人： Guo Jun Ren , Qi Zhang
发明人： Guo Jun Ren , Qi Zhang
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/018528 , H03K19/00369 , H04L25/0272
摘要： An output circuit providing an adjustable output amplitude and common-mode voltage is described. The output circuit includes at least one driver circuit and a common-mode feedback circuit including a first replica circuit of the at least one driver circuit. The common-mode feedback circuit is coupled to receive a first bias and provide an output coupled to the at least one driver circuit. The output circuit may also include a current circuit having a configurable resistor and a second replica circuit of the at least one driver circuit. The current circuit may be coupled to receive a second bias and to provide an output coupled to the at least one driver circuit and the common-mode feedback circuit.
摘要翻译：描述了提供可调输出幅度和共模电压的输出电路。输出电路包括至少一个驱动电路和包括至少一个驱动电路的第一复制电路的共模反馈电路。共模反馈电路被耦合以接收第一偏置并提供耦合到至少一个驱动器电路的输出。输出电路还可以包括具有可配置电阻器的电流电路和至少一个驱动器电路的第二复制电路。当前电路可以被耦合以接收第二偏置并且提供耦合到至少一个驱动器电路和共模反馈电路的输出。

5. 发明授权

US08058924B1 Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device 有权
标题翻译：用于工艺，电压和温度变化的半导体器件的方法和装置
公开(公告)号：US08058924B1
公开(公告)日：2011-11-15
申请号：US12361804
申请日：2009-01-29
申请人： Guo Jun Ren , Prasad Rau , Jian Tan , Qi Zhang
发明人： Guo Jun Ren , Prasad Rau , Jian Tan , Qi Zhang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K19/00384 , G11C29/022 , G11C29/028 , G11C2029/0409 , H03K19/018528
摘要： A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.
摘要翻译：一种降低由于工艺，电压和温度（PVT）和/或其它变化原因导致的基于半导体的器件性能下降的方法和装置。使用自适应反馈机制来感测和纠正性能下降，同时促进诸如可编程逻辑器件（PLD）之类的集成电路（IC）内的可配置性。采用电压反馈机制来检测PVT变化，并自适应调整镜像电流参考以跟踪和基本上消除PVT变化。可以替代地使用多于一个的电压反馈机构来检测差分装置内的基于PVT的变化，由此利用第一电压反馈机构来检测共模电压变化，而第二电压反馈机构产生镜像参考电流基本上消除了共模电压变化，并促进了差动装置的对称运行。

6. 外观设计

USD1041157S1 Lanyard 有权
公开(公告)号：USD1041157S1
公开(公告)日：2024-09-10
申请号：US29934197
申请日：2024-03-25
申请人： Qi Zhang
设计人： Qi Zhang
摘要： The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.
FIG. 1 is a front perspective view of a lanyard showing the new design;
FIG. 2 is a back perspective view thereof;
FIG. 3 is a left-side perspective view thereof;
FIG. 4 is a right-side perspective view thereof,
FIG. 5 is a top view thereof;
FIG. 6 is a bottom view thereof;
FIG. 7 is an enlarged partial view thereof;
FIG. 8 is another enlarged partial view thereof;
FIG. 9 is another perspective view thereof; and,
FIG. 10 is another perspective view thereof.

7. 发明授权

US09299472B2 Copper-alloy barrier layers for metallization in thin-film transistors and flat panel displays 有权
标题翻译：用于薄膜晶体管和平板显示器中金属化的铜合金阻挡层
公开(公告)号：US09299472B2
公开(公告)日：2016-03-29
申请号：US14296796
申请日：2014-06-05
申请人： Shuwei Sun , Francois-Charles Dary , Marc Abouaf , Patrick Hogan , Qi Zhang
发明人： Shuwei Sun , Francois-Charles Dary , Marc Abouaf , Patrick Hogan , Qi Zhang
IPC分类号： H01L21/84 , H01B1/02 , H01L29/66 , G06F3/041 , H01L29/49
CPC分类号： H01L27/1244 , B81C1/00 , B81C1/00031 , B81C1/00404 , B81C1/00523 , B81C1/00547 , C21D1/00 , C21D9/00 , C21D2201/00 , C21D2211/00 , C21D2251/00 , C22F1/00 , C22F1/04 , C22F1/08 , C22F1/14 , G06F3/041 , G06F3/0412 , G06F3/044 , G06F2203/04103 , H01B1/026 , H01L23/53238 , H01L29/4908 , H01L29/6675 , H01L29/78603 , H01L29/78666 , H01L2924/0002 , Y10T428/12611 , Y10T428/1266 , Y10T428/12681 , Y10T428/12687 , Y10T428/12694 , Y10T428/12708 , Y10T428/12715 , Y10T428/12722 , Y10T428/12743 , Y10T428/1275 , Y10T428/12806 , Y10T428/12812 , Y10T428/12819 , Y10T428/12826 , Y10T428/1284 , Y10T428/12847 , Y10T428/12861 , Y10T428/12868 , Y10T428/12875 , Y10T428/12882 , Y10T428/12889 , Y10T428/12896 , Y10T428/12903 , Y10T428/1291 , Y10T428/12931 , H01L2924/00
摘要： In various embodiments, electronic devices such as thin-film transistors incorporate electrodes featuring a conductor layer and, disposed below the conductor layer, a barrier layer comprising an alloy of Cu and one or more refractory metal elements selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr, and Ni.
摘要翻译：在各种实施例中，诸如薄膜晶体管的电子器件包括具有导体层的电极，并且在导体层下方设置阻挡层，该阻挡层包括Cu和一种或多种难熔金属元素的合金，所述难熔金属元素选自Ta，Nb ，Mo，W，Zr，Hf，Re，Os，Ru，Rh，Ti，V，Cr和Ni。

8. 发明授权

US09235500B2 Dynamic memory allocation and relocation to create low power regions 有权
标题翻译：动态内存分配和重定位创建低功耗区域
公开(公告)号：US09235500B2
公开(公告)日：2016-01-12
申请号：US12961519
申请日：2010-12-07
申请人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Swaroop Kavalanekar
发明人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Swaroop Kavalanekar
IPC分类号： G06F11/30 , G06F12/00 , G06F12/02 , G06F1/32
CPC分类号： G06F3/0625 , G06F1/3275 , G06F3/0604 , G06F3/0631 , G06F3/0653 , G06F3/0673 , G06F12/0223 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.
摘要翻译：可以在计算机系统内分配和重新分配存储器对象，以将不经常使用的存储器对象合并到可以以较低功率运行的存储器区域。在记忆对象的初始分配期间，对象可以被放置在高功率区域中。在随后的周期性分析期间，不经常使用的高功率区域中的存储器对象可被重定位到较低功率区域，而经常使用的低功率区域中的存储器对象可能被移动到高功率区域。可以使用各种启发式或逻辑来处理不可移动的对象，共享对象和其他类型的对象。

9. 发明授权

US09062219B2 Superhydrophobic nano-fabrics and coatings 有权
标题翻译：超疏水纳米织物和涂料
公开(公告)号：US09062219B2
公开(公告)日：2015-06-23
申请号：US12356781
申请日：2009-01-21
申请人： Yu Qi , Nan-Xing Hu , Qi Zhang , Gail Song , Sandra Gardner
发明人： Yu Qi , Nan-Xing Hu , Qi Zhang , Gail Song , Sandra Gardner
IPC分类号： G03G13/00 , C09D7/12 , B82Y30/00 , C09D5/16 , G03G15/00 , B82Y40/00 , C08K3/04 , C08K9/08
CPC分类号： C09D7/1291 , B82Y30/00 , B82Y40/00 , C08K3/04 , C08K3/041 , C08K9/08 , C08K2201/016 , C09D5/1662 , C09D7/70 , C09D127/12 , C09D171/00 , C09D179/02 , G03G13/00 , G03G15/00 , G03G15/162 , G03G15/2057 , Y10T428/249979 , Y10T428/25 , Y10T442/2139 , Y10T442/60
摘要： In accordance with the invention, there are articles including hydrophobic composite coating and methods of forming a hydrophobic composite coating. The method of forming a hydrophobic composite coating can include providing a substrate, wherein the substrate can include at least one region. The method can also include providing a dispersion including a plurality of carbon nanotubes, a stabilizer, a hydrophobic polymer, and a solvent, wherein the plurality of carbon nanotubes can be selected from the group consisting of single wall carbon nanotubes and multiple wall carbon nanotubes, and wherein each of the plurality of carbon nanotubes has an aspect ratio of at least about 10. The method can further include applying the dispersion to the one region to form a coated substrate and heating the coated substrate to form a hydrophobic composite coating such that the hydrophobic composite coating has a water contact angle of at least about 120°.
摘要翻译：根据本发明，存在包括疏水复合涂层和形成疏水性复合涂层的方法的制品。形成疏水复合涂层的方法可以包括提供基底，其中基底可以包括至少一个区域。该方法还可以包括提供包括多个碳纳米管，稳定剂，疏水聚合物和溶剂的分散体，其中所述多个碳纳米管可以选自单壁碳纳米管和多壁碳纳米管，并且其中所述多个碳纳米管中的每一个具有至少约10的纵横比。所述方法还可以包括将所述分散体施加到所述一个区域以形成涂覆的基底并加热所述涂覆的基底以形成疏水复合涂层，使得疏水复合涂层具有至少约120°的水接触角。

10. 发明授权

US09050328B2 Pharmaceutical composition for improving dissolution rate of prasugrel and its preparation method 有权
标题翻译：改善普拉格雷溶出率的药物组合物及其制备方法
公开(公告)号：US09050328B2
公开(公告)日：2015-06-09
申请号：US13643197
申请日：2011-04-22
申请人： Junda Cen , Chun-hong Zhang , Qi Zhang , Aifeng Lü
发明人： Junda Cen , Chun-hong Zhang , Qi Zhang , Aifeng Lü
IPC分类号： A61K31/4365 , A61K47/48 , A61K9/14 , A61K9/20 , B82Y5/00 , A61K9/16
CPC分类号： A61K31/4365 , A61K9/145 , A61K9/146 , A61K9/1694 , A61K9/2018 , A61K9/2054 , A61K47/6951 , B82Y5/00
摘要： A pharmaceutical composition containing prasugrel and its pharmaceutically acceptable salts, and methods for preparing the same are disclosed. The pharmaceutical composition improves the dissolution rate of prasugrel and its salts at high pH by using solid dispersion technology, inclusion technology or adding surfactants.
摘要翻译：公开了含有普拉格雷及其药学上可接受的盐的药物组合物及其制备方法。药物组合物通过使用固体分散技术，夹杂物技术或添加表面活性剂，在高pH下改善了普拉格雷及其盐的溶解速率。

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