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1. 发明授权

US5761145A Efficient method for obtaining usable parts from a partially good memory integrated circuit 失效
公开(公告)号：US5761145A
公开(公告)日：1998-06-02
申请号：US685783
申请日：1996-07-24
申请人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
发明人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
IPC分类号： G06F12/16 , G01R31/30 , G06F11/22 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/44 , G11C29/50 , G11C13/00
CPC分类号： G11C29/70 , G01R31/3004 , G06F11/22 , G11C29/02 , G11C29/44 , G11C29/50 , G11C29/83 , G11C29/832 , G11C29/88 , G11C11/401 , G11C2029/5006
摘要： An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.

2. 发明授权

US5838620A Circuit for cancelling and replacing redundant elements 失效
公开(公告)号：US5838620A
公开(公告)日：1998-11-17
申请号：US796148
申请日：1997-02-06
申请人： Paul S. Zagar , Adrian E. Ong
发明人： Paul S. Zagar , Adrian E. Ong
IPC分类号： G11C29/00 , G11C13/00
CPC分类号： G11C29/785 , G11C29/838
摘要： In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynamic random access memory (DRAM) which uses a selectively blowable anti-fuse to disable a redundant element which was previously programmed to replace a defective primary element. The disclosure describes a method for permanently cancelling the defective redundant element and replacing the defective redundant element with another redundant element.

3. 发明授权

US5850368A Burst EDO memory address counter 失效
标题翻译：突发EDO内存地址计数器
公开(公告)号：US5850368A
公开(公告)日：1998-12-15
申请号：US922194
申请日：1997-09-02
申请人： Adrian E. Ong , Paul S. Zagar , Brett L. Williams , Troy A. Manning
发明人： Adrian E. Ong , Paul S. Zagar , Brett L. Williams , Troy A. Manning
IPC分类号： G11C8/04 , G11C8/00
CPC分类号： G11C8/04
摘要： A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.
摘要翻译：由两个触发器和多路复用器组成的计数器产生顺序或交错地址序列。所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。与序列选择信号组合的输入地址被逻辑地组合以产生多路复用器选择输入，其选择第一触发器的真实和补码输出以耦合到第二触发器的输入以指定第二触发器的切换条件。将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化用于另一个突发存取的设备。在脉冲串访问期间读/写控制线的转换将终止脉冲串访问并初始化设备以进行另一个突发存取。

4. 发明授权

US6097647A Efficient method for obtaining usable parts from a partially good memory integrated circuit 有权
标题翻译：从部分良好的存储器集成电路获得可用部件的高效方法
公开(公告)号：US6097647A
公开(公告)日：2000-08-01
申请号：US382526
申请日：1999-08-25
申请人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
发明人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
IPC分类号： G06F12/16 , G01R31/30 , G06F11/22 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/44 , G11C29/50 , G11C7/00
CPC分类号： G11C29/70 , G01R31/3004 , G06F11/22 , G11C29/02 , G11C29/44 , G11C29/50 , G11C29/83 , G11C29/832 , G11C29/88 , G11C11/401 , G11C2029/5006
摘要： An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.
摘要翻译：集成电路存储器件具有多个子阵列分隔，其可以独立地与集成电路上的剩余电路隔离。集成电路的子阵列可以独立测试。如果发现集成电路的子阵列不可操作，则它与集成电路上的剩余电路电隔离，使得其不能干扰剩余电路的正常操作。以前曾经是灾难性的子阵列中的诸如地面短路的电力的缺陷可以电隔离，允许利用剩余的功能子阵列。通过隔离不起作用元件的集成电路修复消除了以前与集成电路相关的电流消耗和其他性能下降，缺陷通过单独使用冗余元件进行维修。

5. 发明授权

US5912579A Circuit for cancelling and replacing redundant elements 有权
标题翻译：用于取消和更换冗余元件的电路
公开(公告)号：US5912579A
公开(公告)日：1999-06-15
申请号：US133586
申请日：1998-08-13
申请人： Paul S. Zagar , Adrian E. Ong
发明人： Paul S. Zagar , Adrian E. Ong
IPC分类号： G11C29/00 , G11C17/16
CPC分类号： G11C29/785 , G11C29/838
摘要： In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynamic random access memory (DRAM) which uses a selectively blowable anti-fuse to disable a redundant element which was previously programmed to replace a defective primary element. The disclosure describes a method for permanently cancelling the defective redundant element and replacing the defective redundant element with another redundant element.
摘要翻译：在具有可寻址主要元件的集成电路和可编程为替代主要元件的冗余元件中，提供了用于取消和替换冗余元件的电路和方法。描述了可以用于存储器中的电路，例如动态随机存取存储器（DRAM），其使用可选择地可吹出的反熔丝来禁用先前被编程为替换有缺陷的主要元件的冗余元件。本公开描述了一种用于永久地消除有缺陷的冗余元件并用另一个冗余元件替换有缺陷的冗余元件的方法。

6. 发明授权

US5677884A Circuit for cancelling and replacing redundant elements 失效
标题翻译：用于取消和更换冗余元件的电路
公开(公告)号：US5677884A
公开(公告)日：1997-10-14
申请号：US816203
申请日：1997-02-28
申请人： Paul S. Zagar , Adrian E. Ong
发明人： Paul S. Zagar , Adrian E. Ong
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/785 , G11C29/838
摘要： In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynamic random access memory (DRAM) which uses a selectively blowable anti-fuse to disable a redundant element which was previously programmed to replace a defective primary element. The disclosure describes a method for permanently cancelling the defective redundant element and replacing the defective redundant element with another redundant element.
摘要翻译：在具有可寻址主要元件的集成电路和可编程为替代主要元件的冗余元件中，提供了用于取消和替换冗余元件的电路和方法。描述了可以用于存储器中的电路，例如动态随机存取存储器（DRAM），其使用可选择地可吹出的反熔丝来禁用先前被编程为替换有缺陷的主要元件的冗余元件。本公开描述了一种用于永久地消除有缺陷的冗余元件并用另一个冗余元件替换有缺陷的冗余元件的方法。

7. 发明授权

US06208568B1 Circuit for cancelling and replacing redundant elements 有权
标题翻译：用于取消和更换冗余元件的电路
公开(公告)号：US06208568B1
公开(公告)日：2001-03-27
申请号：US09133714
申请日：1998-08-13
申请人： Paul S. Zagar , Adrian E. Ong
发明人： Paul S. Zagar , Adrian E. Ong
IPC分类号： G11C1300
CPC分类号： G11C29/785 , G11C29/838
摘要： In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynamic random access memory (DRAM) which uses a selectively blowable anti-fuse to disable a redundant element which was previously programmed to replace a defective primary element. The disclosure describes a method for permanently cancelling the defective redundant element and replacing the defective redundant element with another redundant element.
摘要翻译：在具有可寻址主要元件的集成电路和可编程为替代主要元件的冗余元件中，提供了用于取消和替换冗余元件的电路和方法。描述了可以用于存储器中的电路，例如动态随机存取存储器（DRAM），其使用可选择地可吹出的反熔丝来禁用先前被编程为替换有缺陷的主要元件的冗余元件。本公开描述了一种用于永久地消除有缺陷的冗余元件并用另一个冗余元件替换有缺陷的冗余元件的方法。

8. 再颁专利

USRE36821E Wordline driver circuit having a directly gated pull-down device 失效
标题翻译：字线驱动电路具有直接门控下拉装置
公开(公告)号：USRE36821E
公开(公告)日：2000-08-15
申请号：US644351
申请日：1996-05-10
申请人： Stephen L. Casper , Paul S. Zagar , Adrian E. Ong
发明人： Stephen L. Casper , Paul S. Zagar , Adrian E. Ong
IPC分类号： G11C8/00 , G11C8/08
CPC分类号： G11C8/08
摘要： The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The driving device is electrically interposed between the wordline and a reference node. The invention provides low power operation, and provides reliable wordline selection for circuits having supply potentials less than 5 volts.
摘要翻译：本发明是用于快速驱动未选择的字线以纠正电位的电路和方法。本发明通过由解码电路产生的初级选择预解码信号直接选通的驱动装置将未选择的字线驱动到低电位。驱动装置电插入字线和参考节点之间。本发明提供低功率操作，并且为电源电压低于5伏的电路提供可靠的字线选择。

9. 发明授权

US5970008A Efficient method for obtaining usable parts from a partially good memory integrated circuit 失效
公开(公告)号：US5970008A
公开(公告)日：1999-10-19
申请号：US993824
申请日：1997-12-18
申请人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
发明人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
IPC分类号： G06F12/16 , G01R31/30 , G06F11/22 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/44 , G11C29/50 , G11C7/00
CPC分类号： G11C29/70 , G01R31/3004 , G06F11/22 , G11C29/02 , G11C29/44 , G11C29/50 , G11C29/83 , G11C29/832 , G11C29/88 , G11C11/401 , G11C2029/5006
摘要： An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.

10. 发明授权

US5488583A Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits 失效
标题翻译：具有片上拓扑逻辑驱动器的存储器集成电路，以及用于测试和产生这种存储器集成电路的方法
公开(公告)号：US5488583A
公开(公告)日：1996-01-30
申请号：US311582
申请日：1994-09-22
申请人： Adrian E. Ong , William K. Waller , Paul S. Zagar
发明人： Adrian E. Ong , William K. Waller , Paul S. Zagar
IPC分类号： G11C7/10 , G11C7/18 , G11C29/36 , G11C7/00 , G11C29/00
CPC分类号： G11C29/36 , G11C7/1006 , G11C7/18
摘要： A memory integrated circuit chip of a predefined circuit topology has an on-chip topology logic driver. The topology logic driver selectively inverts data being written to and read from addressed memory cells in the memory IC based upon location of the addressed memory cells in the circuit topology of the memory array. The topology logic driver is preferably a logic circuit that embodies a boolean function defining the circuit topology. A method for testing and producing such memory ICs is also described.
摘要翻译：预定义电路拓扑的存储器集成电路芯片具有片上拓扑逻辑驱动器。拓扑逻辑驱动器基于存储器阵列的电路拓扑中寻址的存储器单元的位置选择性地反转正在写入存储器IC中的寻址存储器单元的数据和从其读出的数据。拓扑逻辑驱动器优选地是实现定义电路拓扑的布尔函数的逻辑电路。还描述了用于测试和产生这种存储器IC的方法。

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