专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130182998A1 SILICON PHOTONIC CHIP OPTICAL COUPLING STRUCTURES 有权
标题翻译：硅光电芯片光耦合结构
公开(公告)号：US20130182998A1
公开(公告)日：2013-07-18
申请号：US13353118
申请日：2012-01-18
申请人： Paul S. Andry , Russell A. Budd , Frank R. Libsch , Robert L. Wisnieff
发明人： Paul S. Andry , Russell A. Budd , Frank R. Libsch , Robert L. Wisnieff
IPC分类号： G02B6/42 , G02B6/32
CPC分类号： G02B6/4204 , G02B6/34
摘要： A silicon photonic chip is provided. An active silicon layer that includes a photonic device is on a front side of the silicon photonic chip. A silicon substrate that includes an etched backside cavity is on a backside of the silicon photonic chip. A microlens is integrated into the etched backside cavity. A buried oxide layer is located between the active silicon layer and the silicon substrate. The buried oxide layer is an etch stop for the etched backside cavity.
摘要翻译：提供硅光子芯片。包括光子器件的有源硅层位于硅光子芯片的前侧。包括蚀刻的背面腔的硅衬底位于硅光子芯片的背面。将微透镜集成到蚀刻的背面腔中。掩埋氧化物层位于有源硅层和硅衬底之间。掩埋氧化物层是用于蚀刻的背面腔的蚀刻停止。

2. 发明授权

US08855452B2 Silicon photonic chip optical coupling structures 有权
标题翻译：硅光子芯片光耦合结构
公开(公告)号：US08855452B2
公开(公告)日：2014-10-07
申请号：US13353118
申请日：2012-01-18
申请人： Paul S. Andry , Russell A. Budd , Frank R. Libsch , Robert L. Wisnieff
发明人： Paul S. Andry , Russell A. Budd , Frank R. Libsch , Robert L. Wisnieff
IPC分类号： G02B6/34 , G02B6/12
CPC分类号： G02B6/4204 , G02B6/34
摘要： A silicon photonic chip is provided. An active silicon layer that includes a photonic device is on a front side of the silicon photonic chip. A silicon substrate that includes an etched backside cavity is on a backside of the silicon photonic chip. A microlens is integrated into the etched backside cavity. A buried oxide layer is located between the active silicon layer and the silicon substrate. The buried oxide layer is an etch stop for the etched backside cavity.
摘要翻译：提供硅光子芯片。包括光子器件的有源硅层位于硅光子芯片的前侧。包括蚀刻的背面腔的硅衬底位于硅光子芯片的背面。将微透镜集成到蚀刻的背面腔中。掩埋氧化物层位于有源硅层和硅衬底之间。掩埋氧化物层是用于蚀刻的背面腔的蚀刻停止。

3. 发明申请

US20110044369A1 SILICON CARRIER OPTOELECTRONIC PACKAGING 有权
标题翻译：硅载体光电包装
公开(公告)号：US20110044369A1
公开(公告)日：2011-02-24
申请号：US12544696
申请日：2009-08-20
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
IPC分类号： H01S5/18 , H01L31/0232 , H01L23/34 , H01L21/50
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

4. 发明授权

US08290008B2 Silicon carrier optoelectronic packaging 有权
标题翻译：硅载光子包装
公开(公告)号：US08290008B2
公开(公告)日：2012-10-16
申请号：US12544696
申请日：2009-08-20
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
IPC分类号： H01S5/022 , H01S5/024
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

5. 发明申请

US20120326290A1 SILICON CARRIER OPTOELECTRONIC PACKAGING 有权
标题翻译：硅载体光电包装
公开(公告)号：US20120326290A1
公开(公告)日：2012-12-27
申请号：US13604341
申请日：2012-09-05
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chrirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chrirag S. Patel
IPC分类号： H01L23/34 , H01L21/50
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

6. 发明授权

US06566687B2 Metal induced self-aligned crystallization of Si layer for TFT 有权
标题翻译： TFT的Si层的金属诱导自对准结晶
公开(公告)号：US06566687B2
公开(公告)日：2003-05-20
申请号：US09765134
申请日：2001-01-18
申请人： Paul S. Andry , Frank R. Libsch , Takatoshi Tsujimura
发明人： Paul S. Andry , Frank R. Libsch , Takatoshi Tsujimura
IPC分类号： H01L2904
CPC分类号： H01L29/78633 , H01L21/0237 , H01L21/02532 , H01L21/02672 , H01L27/12 , H01L27/1277 , H01L29/66757
摘要： The present invention discloses a semiconductor device, a thin film transistor (TFT), and a process for forming a TFT. The semiconductor device according to the present invention comprises a top-gate type thin film transistor (TFT), said top-gate type TFT being formed on a substrate, said top-gate type TFT comprising: an insulating layer deposited on said substrate; a source electrode and a drain electrode formed from a metal-dopant compound, said metal-dopant compound being deposited on said insulating layer; a polycrystalline Si (poly-Si) layer deposited on said insulating layer and said source electrode and said drain electrode; an ohmic contact layer being formed between said metal-dopant compound and said poly-Si layer through migration of said dopant from said metal-dopant compound; a gate insulating layer deposited on said poly-Si layer; and a gate electrode formed on said gate insulating layer, wherein said poly-Si layer is crystallized by metal induced lateral crystallization.
摘要翻译：本发明公开了半导体器件，薄膜晶体管（TFT）和TFT的形成工艺。根据本发明的半导体器件包括顶栅型薄膜晶体管（TFT），所述顶栅型TFT形成在衬底上，所述顶栅型TFT包括：沉积在所述衬底上的绝缘层; 由金属 - 掺杂剂化合物形成的源电极和漏电极，所述金属 - 掺杂剂化合物沉积在所述绝缘层上; 沉积在所述绝缘层和所述源电极和所述漏电极上的多晶Si（多晶硅）层; 通过所述掺杂剂从所述金属掺杂剂化合物的迁移，在所述金属 - 掺杂剂化合物和所述多晶硅层之间形成欧姆接触层; 沉积在所述多晶硅层上的栅极绝缘层; 以及形成在所述栅极绝缘层上的栅电极，其中所述多晶硅层通过金属诱导的横向结晶而结晶。

7. 发明授权

US06338988B1 Method for fabricating self-aligned thin-film transistors to define a drain and source in a single photolithographic step 有权
标题翻译：用于在单个光刻步骤中制造自对准薄膜晶体管以限定漏极和源极的方法
公开(公告)号：US06338988B1
公开(公告)日：2002-01-15
申请号：US09410280
申请日：1999-09-30
申请人： Paul S. Andry , Frank R. Libsch
发明人： Paul S. Andry , Frank R. Libsch
IPC分类号： H01L2100
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/42384 , H01L29/4908 , H01L29/66765 , H01L29/78696
摘要： A method for forming a thin film transistor having source and drain electrodes self-aligned to a gate electrode by employing a single lithographic step includes forming an opaque gate electrode on a substrate, depositing a first dielectric layer on the gate electrode and the substrate, depositing a semiconductor layer on the first dielectric layer, and depositing a second dielectric layer on the semiconductor layer. A first photoresist is deposited on the second dielectric layer and patterned by employing the gate electrode as a mask for blocking light used to expose the first photoresist. The second dielectric layer is etched to form a top insulator portion of the second dielectric layer in alignment with the gate electrode. The first photoresist is removed. A doped semiconductor layer and a conductive layer are deposited. A second photoresist is formed on the conductive layer. The second photoresist is patterned to form components patterns and to form a contiguous transistor electrode pattern covering the top insulator portion. Non-selectively etching the second photoresist and the conductive layer, a gap is formed in the second photoresist for the transistor electrode pattern at the top insulator portion. The conductive layer and the doped semiconductor layer are etched selective to the second photoresist such that a source electrode and a drain electrode are formed which are self-aligned relative to the gate electrode.
摘要翻译：一种用于形成具有通过采用单个光刻步骤自对准到栅电极的源电极和漏电极的薄膜晶体管的方法包括在衬底上形成不透明栅电极，在栅电极和衬底上沉积第一介电层，沉积在所述第一电介质层上的半导体层，以及在所述半导体层上沉积第二电介质层。第一光致抗蚀剂沉积在第二介电层上，并通过采用栅电极作为遮挡用于曝光第一光致抗蚀剂的光的掩模进行图案化。蚀刻第二电介质层以形成与栅极电极对准的第二电介质层的顶部绝缘体部分。去除第一光致抗蚀剂。沉积掺杂半导体层和导电层。在导电层上形成第二光致抗蚀剂。图案化第二光致抗蚀剂以形成部件图案并形成覆盖顶部绝缘体部分的连续晶体管电极图案。非选择性地蚀刻第二光致抗蚀剂和导电层，在顶部绝缘体部分处的晶体管电极图案的第二光致抗蚀剂中形成间隙。对第二光致抗蚀剂选择性地蚀刻导电层和掺杂半导体层，使得形成相对于栅电极自对准的源电极和漏电极。

8. 发明授权

US06580127B1 High performance thin film transistor and active matrix process for flat panel displays 有权
标题翻译：用于平板显示器的高性能薄膜晶体管和有源矩阵工艺
公开(公告)号：US06580127B1
公开(公告)日：2003-06-17
申请号：US09409157
申请日：1999-09-30
申请人： Paul S. Andry , Frank R. Libsch
发明人： Paul S. Andry , Frank R. Libsch
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L27/12 , H01L29/4908 , H01L29/66765 , H01L29/78618 , H01L29/78669
摘要： A transistor, in accordance with the present inventions includes a gate electrode layer formed on a substrate and an insulating layer formed on the gate electrode layer. A first conductive layer forms a first portion and a second portion separated by a gap therebetween. The gap is formed at a position corresponding to a gate electrode in the gate electrode layer. A doping layer is formed on the first portion and the second portion of the first conductive layer, forming a source and a drain for the transistor. A semiconductor layer is formed over the doping layer of the first portion and the second portion and in the gap in contact with the insulating layer such that upon activation of the gate electrode current flows across the gap directly between the first portion and the second portion in the first conductive layer. Methods for fabrication and other embodiments are also included.
摘要翻译：根据本发明的晶体管包括形成在基板上的栅电极层和形成在栅电极层上的绝缘层。第一导电层形成第一部分和由它们之间的间隙隔开的第二部分。间隙形成在与栅电极层中的栅电极对应的位置处。在第一导电层的第一部分和第二部分上形成掺杂层，形成晶体管的源极和漏极。半导体层形成在第一部分和第二部分的掺杂层上，并且在与绝缘层接触的间隙中，使得在激活栅极电极时，电流在第一部分和第二部分之间直接流过间隙第一导电层。还包括制造方法和其他实施例。

9. 发明授权

US08559474B2 Silicon carrier optoelectronic packaging 有权
标题翻译：硅载光子包装
公开(公告)号：US08559474B2
公开(公告)日：2013-10-15
申请号：US13604341
申请日：2012-09-05
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank F. Libsch , Sylvain Ouimet , Chrirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank F. Libsch , Sylvain Ouimet , Chrirag S. Patel
IPC分类号： H01S5/024 , H01S5/18 , H01L23/28 , H01L23/18
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

10. 发明授权

US08440544B2 CMOS structure and method of manufacture 失效
标题翻译： CMOS结构及制造方法
公开(公告)号：US08440544B2
公开(公告)日：2013-05-14
申请号：US12899127
申请日：2010-10-06
申请人： Paul S. Andry , Edmund J. Sprogis , Cornelia K. Tsang
发明人： Paul S. Andry , Edmund J. Sprogis , Cornelia K. Tsang
IPC分类号： H01L21/301
CPC分类号： H01L29/06 , H01L21/2007 , H01L21/6835 , H01L21/76251 , H01L21/8221 , H01L27/0688 , H01L2221/68368 , H01L2221/68381 , H01L2924/00011 , H01L2224/80001
摘要： CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding structure.
摘要翻译：具有替代衬底的CMOS结构和制造方法在本文中公开。该方法包括在临时衬底上形成器件。该方法还包括移除临时衬底。所述方法还包括用固定结构将永久电绝缘衬底粘合到所述器件上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式