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1. 发明授权

US08328156B2 Techniques for forming solder bump interconnects 有权
标题翻译：形成焊料凸块互连的技术
公开(公告)号：US08328156B2
公开(公告)日：2012-12-11
申请号：US13371840
申请日：2012-02-13
申请人： Bing Dang , Peter A. Gruber , Luc Guerin , Chirag S. Patel
发明人： Bing Dang , Peter A. Gruber , Luc Guerin , Chirag S. Patel
IPC分类号： B28B7/22 , E04G11/50
CPC分类号： B23K1/0016 , B23K3/0623 , B23K2101/40 , H01L24/11 , H01L2224/11003 , H01L2224/11334 , H01L2224/16225 , H01L2924/00013 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2224/29099 , H01L2924/00
摘要： Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.
摘要翻译：通过执行几个步骤在晶片的附接点上形成互连。在半导体衬底中形成具有预定形状的多个空腔。然后用互连材料填充这些空腔以形成互连。互连随后连接到晶片的附接点。

2. 发明申请

US20120301977A1 SILICON CARRIER STRUCTURE AND METHOD OF FORMING SAME 审中-公开
标题翻译：硅载体结构及其形成方法
公开(公告)号：US20120301977A1
公开(公告)日：2012-11-29
申请号：US13569872
申请日：2012-08-08
申请人： Paul Stephen Andry , Harm Peter Hofstee , George A. Katopis , John Ulrich Knickerbocker , Robert K. Montoye , Chirag S. Patel
发明人： Paul Stephen Andry , Harm Peter Hofstee , George A. Katopis , John Ulrich Knickerbocker , Robert K. Montoye , Chirag S. Patel
IPC分类号： H01L21/66 , G06F17/50
CPC分类号： H01L25/0655 , H01L23/147 , H01L23/60 , H01L25/0652 , H01L2224/16225 , H01L2924/10253 , H01L2924/157 , H01L2924/00
摘要： A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.
摘要翻译：一种用于电子封装的硅载体结构包括基底，设置在基底基板上的硅载体衬底，设置在硅载体衬底上的存储芯片，设置在硅载体衬底上的微处理器芯片，设置在硅衬底上的输入/输出芯片硅载体衬底和设置在硅载体衬底上的时钟芯片。

3. 发明授权

US08290008B2 Silicon carrier optoelectronic packaging 有权
标题翻译：硅载光子包装
公开(公告)号：US08290008B2
公开(公告)日：2012-10-16
申请号：US12544696
申请日：2009-08-20
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
IPC分类号： H01S5/022 , H01S5/024
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

4. 发明授权

US08148255B2 Techniques for forming solder bump interconnects 有权
公开(公告)号：US08148255B2
公开(公告)日：2012-04-03
申请号：US11856831
申请日：2007-09-18
申请人： Bing Dang , Peter A. Gruber , Luc Guerin , Chirag S. Patel
发明人： Bing Dang , Peter A. Gruber , Luc Guerin , Chirag S. Patel
IPC分类号： H01L21/44
CPC分类号： B23K1/0016 , B23K3/0623 , B23K2101/40 , H01L24/11 , H01L2224/11003 , H01L2224/11334 , H01L2224/16225 , H01L2924/00013 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2224/29099 , H01L2924/00
摘要： Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

5. 发明授权

US07352066B2 Silicon based optical vias 有权
标题翻译：硅基光通孔
公开(公告)号：US07352066B2
公开(公告)日：2008-04-01
申请号：US10675139
申请日：2003-09-30
申请人： Russell A. Budd , Punit P. Chiniwalla , Chirag S. Patel
发明人： Russell A. Budd , Punit P. Chiniwalla , Chirag S. Patel
IPC分类号： H01L23/48
CPC分类号： G02B6/43 , H01L23/481 , H01L2924/0002 , H05K1/0274 , H01L2924/00
摘要： Method of fabricating a semiconductor die with a microlens associated therewith. More particularly, a method for fabricating a vertical channel guide optical via through a silicon substrate wherein the optical via can contain lens elements, a discrete index gradient guiding pillar and other embodiments. Also disclosed are means for transferring, coupling and or focusing light from an electronic-optical device on the top of a semiconductor substrate through the substrate to a waveguiding medium below the substrate. The high alignment accuracies afforded by standard semiconductor fabrication processes are exploited so as to obviate the need for active alignment of the optical coupling or light guiding elements.
摘要翻译：制造具有与之相关联的微透镜的半导体管芯的方法。更具体地，涉及一种通过硅衬底制造垂直沟道引导光通孔的方法，其中光通孔可以包含透镜元件，离散折射率梯度引导柱和其它实施例。还公开了用于将来自半导体衬底顶部的电子光学器件的光通过衬底转移，耦合和聚焦到衬底下面的波导介质的装置。利用由标准半导体制造工艺提供的高对准精度，以便消除对光学耦合或导光元件的主动对准的需要。

6. 发明授权

US06528349B1 Monolithically-fabricated compliant wafer-level package with wafer level reliability and functionality testability 失效
标题翻译：具有晶圆级可靠性和功能可测性的单片制造兼容晶圆级封装
公开(公告)号：US06528349B1
公开(公告)日：2003-03-04
申请号：US09697031
申请日：2000-10-26
申请人： Chirag S. Patel , Kevin Martin , James D. Meindl
发明人： Chirag S. Patel , Kevin Martin , James D. Meindl
IPC分类号： H01L2144
CPC分类号： H01L23/3114 , H01L24/02 , H01L24/11 , H01L24/12 , H01L24/16 , H01L2224/0231 , H01L2224/0233 , H01L2224/0235 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/1147 , H01L2224/13022 , H01L2224/13116 , H01L2924/00013 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2224/13099
摘要： Compliant wafer level packages 10 and methods for monolithically fabricating the same. A monolithically fabricated compliant wafer level package 10 having a compliant layer 14 and a compliant interconnect 30 passing therein. The compliant interconnects 30 being provided so that electrical and mechanical connections may be supported across the compliant layer 14, and constructed so that stresses related to relative motion between electrical components is accommodated. A method of providing a substrate 10 having a compliant layer 14, the compliant layer 14 having a via 20 that exposes a die pad 12 on the substrate 10. Fabricating a compliant interconnect 30 so that the compliant interconnect 30 contacts the die pad 12. The compliant interconnect 30 constructed so that electrical and mechanical connections may be supported through the compliant layer 14.
摘要翻译：符合标准的晶圆级封装10及其整体制造方法。具有柔性层14和通过其中的顺应性互连30的单片制造的柔性晶片级封装10。柔性互连件30被设置成使得电气和机械连接可跨越顺应性层14被支撑，并被构造成使得与电气部件之间的相对运动相关的应力被容纳。一种提供具有柔性层14的衬底10的方法，柔性层14具有通孔20，该通孔20使衬底10上的管芯焊盘12暴露出来。制造柔性互连件30，使柔性互连件30与管芯焊盘12接触。被构造成使得电气和机械连接可以通过柔性层14被支撑。

7. 发明授权

US09119164B2 Generating access point beacons at different power levels 有权
标题翻译：在不同的功率级别生成接入点信标
公开(公告)号：US09119164B2
公开(公告)日：2015-08-25
申请号：US12542294
申请日：2009-08-17
申请人： Mehmet Yavuz , Sanjiv Nanda , Manoj M. Deshpande , Chirag S. Patel
发明人： Mehmet Yavuz , Sanjiv Nanda , Manoj M. Deshpande , Chirag S. Patel
IPC分类号： H04W4/00 , H04W52/32 , H04W52/24 , H04W52/28 , H04W84/04
CPC分类号： H04W52/325 , H04W52/244 , H04W52/245 , H04W52/28 , H04W84/045
摘要： An access point generates beacons at different power levels at different times to provide an acceptable tradeoff between coverage area associated with the beacons and outage experienced at nearby access terminals. For example, a femto access point may transmit beacons at a relatively low power for a relatively long period of time to reduce interference at nearby access terminals that are being served by a macro access point. The femto access point may then transmit beacons at a relatively high power for a relatively short period of time to enable nearby access terminals to receive the beacons. Also, a given transmit chain may be used to provide frequency hopping of high and low power beacons.
摘要翻译：接入点在不同时间产生不同功率电平的信标，以提供与信标相关联的覆盖区域和在附近接入终端处经历的中断之间的可接受的折中。例如，毫微微接入点可以以相对较低的功率在相对长的时间段内发送信标，以减少正在由宏接入点服务的附近接入终端的干扰。毫微微接入点然后可以在相对较短的时间段内以相对高的功率发送信标，以使附近的接入终端能够接收信标。此外，给定的发射链可以用于提供高和低功率信标的跳频。

8. 发明授权

US08755644B2 Silicon based optical vias 有权
标题翻译：硅基光通孔
公开(公告)号：US08755644B2
公开(公告)日：2014-06-17
申请号：US12080266
申请日：2008-04-01
申请人： Russell A. Budd , Punit P. Chiniwalla , Chirag S. Patel
发明人： Russell A. Budd , Punit P. Chiniwalla , Chirag S. Patel
IPC分类号： G02B6/12 , H01L21/00 , H01L23/48
CPC分类号： G02B6/4206 , G02B6/4214 , H01L33/58 , H01S5/005 , H01S5/02248 , H01S5/02288 , H01S5/183
摘要： Method of fabricating a semiconductor die with a microlens associated therewith. More particularly, a method for fabricating a vertical channel guide optical via through a silicon substrate wherein the optical via can contain lens elements, a discrete index gradient guiding pillar and other embodiments. Also disclosed are means for transferring, coupling and or focusing light from an electronic-optical device on the top of a semiconductor substrate through the substrate to a waveguiding medium below the substrate. The high alignment accuracies afforded by standard semiconductor fabrication processes are exploited so as to obviate the need for active alignment of the optical coupling or light guiding elements.
摘要翻译：制造具有与之相关联的微透镜的半导体管芯的方法。更具体地，涉及一种通过硅衬底制造垂直沟道引导光通孔的方法，其中光通孔可以包含透镜元件，离散折射率梯度引导柱和其它实施例。还公开了用于将来自半导体衬底顶部的电子光学器件的光通过衬底转移，耦合和聚焦到衬底下面的波导介质的装置。利用由标准半导体制造工艺提供的高对准精度，以便消除对光学耦合或导光元件的主动对准的需要。

9. 发明授权

US08405226B2 Semiconductor device and method of making semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US08405226B2
公开(公告)日：2013-03-26
申请号：US13495195
申请日：2012-06-13
申请人： John U. Knickerbocker , Chirag S. Patel
发明人： John U. Knickerbocker , Chirag S. Patel
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5286 , H01L21/486 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/50 , H01L25/0652 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2924/12044 , H01L2924/1461 , H01L2924/15311 , H01L2924/00
摘要： A method of fabricating a semiconductor device including forming a micro-chip comprising a thinned-wafer having one or more components fabricated thereon disposed between a carrier and a semiconductor chip, the micro-chip being electrically connected to the semiconductor chip under a higher consumption macro of the semiconductor chip and including a thickness which is less than a thickness of the semiconductor chip, forming an interconnect between the semiconductor chip and the carrier, forming an interconnect between the micro-chip and the semiconductor chip, and forming an interconnect between the micro-chip and the carrier. The micro-chip includes a thinned micro-chip having a thickness of less than 20 microns and the semiconductor chip includes plural semiconductor chips formed as a chip stack. The micro-chip includes a plurality of micro-chips formed on the plural semiconductor chips, such that the semiconductor device is a three-dimensional integrated circuit.
摘要翻译：一种制造半导体器件的方法，包括形成包括在其上制造的一个或多个部件的薄化晶片的微型芯片，所述薄片晶片设置在载体和半导体芯片之间，所述微芯片在较高功耗的宏观下电连接到所述半导体芯片并且包括小于半导体芯片的厚度的厚度，在半导体芯片和载体之间形成互连，在微芯片和半导体芯片之间形成互连，并且在微型芯片和微型芯片之间形成互连芯片和载体。微芯片包括厚度小于20微米的薄化微芯片，半导体芯片包括形成为芯片堆叠的多个半导体芯片。微芯片包括形成在多个半导体芯片上的多个微芯片，使得半导体器件是三维集成电路。

10. 发明授权

US07518225B2 Chip system architecture for performance enhancement, power reduction and cost reduction 有权
标题翻译：芯片系统架构，用于性能提升，功耗降低和成本降低
公开(公告)号：US07518225B2
公开(公告)日：2009-04-14
申请号：US11538567
申请日：2006-10-04
申请人： Philip G. Emma , John U. Knickerbocker , Chirag S. Patel
发明人： Philip G. Emma , John U. Knickerbocker , Chirag S. Patel
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/642 , H01L25/0652 , H01L25/18 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A computer chip is structured to have at least one single-layered chip, at least one multi-layered chip stack, and a carrier package characterized by electrical interconnections of less than 100 microns diameter, wherein the single-layered chip and the multi-layered chip stack are each electrically coupled to the electrical interconnections of the carrier package, and the single-layered chip is communicatively coupled to the multi-layered chip stack through the carrier package so that an electrical signal propagates over a given distance between the single-layered chip and the multi-layered chip stack at substantially a speed of propagation for a single layer chip over the given distance. The single-layered chip can be a processor having multi-cores and the multi-layered chip stack can be a memory cache stack. Interconnect vias, having a density at least as great as 2500 interconnects/cm2 electrically couple the single-layered chip and the multi-layered chip stack to the carrier package.
摘要翻译：计算机芯片被构造成具有至少一个单层芯片，至少一个多层芯片堆叠和以小于100微米直径的电互连为特征的载体封装，其中单层芯片和多层芯片芯片堆叠都电耦合到载体封装的电互连，并且单层芯片通过载体封装通信地耦合到多层芯片堆叠，使得电信号在单层之间传递给定距离芯片和多层芯片堆栈，在给定距离内的单层芯片基本上是传播速度。单层芯片可以是具有多核的处理器，并且多层芯片堆栈可以是存储器高速缓存堆栈。具有至少高达2500个互连/ cm2的密度的互连通孔将单层芯片和多层芯片堆叠电耦合到载体封装。

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