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    • 2. 发明授权
    • Method of making a transistor array
    • 制造晶体管阵列的方法
    • US4282646A
    • 1981-08-11
    • US68282
    • 1979-08-20
    • Andres G. FortinoHenry J. Geipel, Jr.Lawrence G. HellerRonald Silverman
    • Andres G. FortinoHenry J. Geipel, Jr.Lawrence G. HellerRonald Silverman
    • H01L21/822G11C11/56G11C17/12H01L21/225H01L21/8246H01L27/04H01L27/112H01L29/78H01L21/26
    • H01L27/11266G11C11/56G11C11/5692G11C17/12H01L21/2253H01L27/112
    • A method of making a transistor array includes forming a plurality of gate electrodes insulated from a semiconductor substrate having an impurity of a given conductivity, introducing a first impurity having a conductivity opposite to that of the given conductivity into a given region of the substrate which is adjacent to an edge of each of the gate electrodes, introducing a second impurity having the given conductivity into given regions adjacent to selected gate electrodes, the second impurity having a significantly higher diffusivity than that of the first impurity in the semiconductor substrate, and driving the second impurity along the surface of the semiconductor substrate to form in the substrate under each of the selected gate electrodes a region having a concentration of impurity of the given conductivity higher than that of the semiconductor substrate. The transistor array may be used, e.g. to make a read only memory (ROM) by connecting appropriate current sensing means to each of the given regions to indicate the presence or absence of the higher diffusivity impurity when a predetermined voltage is applied to the gate electrodes. In one embodiment, the semiconductor substrate is made of P type conductivity, the first impurity is arsenic which produces N type conductivity regions and the second impurity is boron, which produces P type conductivity. Since boron has a higher diffusivity than arsenic, after they are driven by heating the boron impurity produces a high threshold region under the gate electrode when introduced in sufficiently high concentration.
    • 制造晶体管阵列的方法包括形成与具有给定导电性的杂质的半导体衬底绝缘的多个栅电极,将具有与所述导电性相反的导电性的第一杂质引入衬底的给定区域 与每个栅电极的边缘相邻,将具有给定导电性的第二杂质引入到与所选择的栅电极相邻的给定区域中,第二杂质具有比半导体衬底中的第一杂质显着更高的扩散率,并驱动 沿着半导体衬底的表面形成第二杂质,以在所选择的栅电极的每一个下的衬底中形成具有比半导体衬底的导电性高的给定导电性的杂质浓度的区域。 可以使用晶体管阵列,例如, 通过将适当的电流感测装置连接到每个给定区域来形成只读存储器(ROM),以指示当将预定电压施加到栅电极时存在或不存在较高扩散性杂质。 在一个实施例中,半导体衬底由P型导电性制成,第一杂质是产生N型导电区域的砷,第二杂质是硼,产生P型导电性。 由于硼具有比砷更高的扩散性,因此通过加热驱动硼杂质,当以足够高的浓度引入时,在栅电极下产生高阈值区域。
    • 8. 发明授权
    • Simple process for making complementary transistors
    • 制造互补晶体管的简单过程
    • US4480375A
    • 1984-11-06
    • US448124
    • 1982-12-09
    • Peter E. CottrellHenry J. Geipel, Jr.
    • Peter E. CottrellHenry J. Geipel, Jr.
    • H01L27/092H01L21/8238H01L29/78H01L21/22H01L21/263
    • H01L21/823814Y10S438/981
    • A very simple process is provided, with reduced processing time, for making a CMOS structure using a single polysilicon, or other refractory metal, layer which includes forming a thin gate oxide on both N and P type semiconductor layers of a common substrate, forming a gate electrode simultaneously on the N type and on the P type layers and selectively implanting an N type impurity to form N+ source and drain regions in the P type layer. The semiconductor layers are then oxidized to form substantially thicker oxide, such a silicon dioxide, adjacent to the sides of the gate electrode over the P type layer than the thickness of the oxide adjacent to the sides of the gate electrode over the N type layer. Without using a mask, a P type impurity is implanted into the N type layer to form P+ source and drain regions.
    • 提供了一种非常简单的方法,缩短了处理时间,用于制造使用单个多晶硅的CMOS结构或其它难熔金属层,其包括在公共基板的N型和P型半导体层上形成薄的栅极氧化物,形成 栅电极同时在N型和P型层上,并且选择性地注入N型杂质以在P型层中形成N +源极和漏极区。 然后氧化氧化半导体层以形成比在N型层上与栅电极相邻的氧化物的厚度相邻的,比P型层更靠近栅电极侧面的基本上较厚的氧化物,例如二氧化硅。 在不使用掩模的情况下,将P型杂质注入到N型层中以形成P +源极和漏极区。
    • 9. 发明授权
    • Method of fabricating a highly conductive structure
    • 制造高导电结构的方法
    • US4398341A
    • 1983-08-16
    • US304436
    • 1981-09-21
    • Henry J. Geipel, Jr.Larry A. Nesbit
    • Henry J. Geipel, Jr.Larry A. Nesbit
    • H01L29/78H01L21/027H01L21/28H01L21/3205H01L21/321H01L21/768H01L23/52H01L29/423H01L29/43H01L29/49H01L21/285
    • H01L21/0272H01L21/28097H01L21/28123H01L21/321H01L21/7688H01L21/76889Y10S438/951
    • An improved method of fabricating a silicide structure includes depositing a metal, e.g., molybdenum or tungsten, directly onto a thin insulating layer of silicon dioxide and/or silicon nitride formed on a semiconductor substrate, co-depositing the metal and silicon onto the metal layer and then depositing silicon onto the co-deposited metal-silicon layer. This structure is annealed at a temperature sufficient to form a metal silicide between the thin insulating layer and the layer of silicon. The silicon layer serves as a source of silicon for the metal layer which is consumed during the annealing step to form, along with the co-deposited metal-silicon layer, a relatively thick metal silicide layer directly on the thin silicon dioxide layer. A sufficiently thick silicon layer is initially provided on the co-deposited metal-silicon layer so that a portion of the initial silicon layer remains after the annealing step has been completed. This excess silicon may be oxidized to form a passivating layer on top of the thick metal silicide layer. If all or a part of the silicon in the remaining silicon layer after annealing is removed, the thick metal silicide layer may be exposed to an oxidizing ambient for self-passivation. In this latter instance, the pure metal precipitates in the silicide resulting in a line with even greater conductivity than a pure silicide line, which is very desirable for interconnections.
    • 制造硅化物结构的改进方法包括将金属(例如钼或钨)直接沉积到半导体衬底上形成的二氧化硅和/或氮化硅的薄绝缘层上,将金属和硅共沉积到金属层上 然后在共沉积的金属硅层上沉积硅。 该结构在足以在薄绝缘层和硅层之间形成金属硅化物的温度下退火。 硅层用作用于金属层的硅源,其在退火步骤期间消耗,以与共沉积的金属硅层一起形成直接在薄二氧化硅层上的相对厚的金属硅化物层。 最初在共沉积的金属 - 硅层上提供足够厚的硅层,使得在退火步骤完成之后残留初始硅层的一部分。 该多余的硅可被氧化以在厚金属硅化物层的顶部形成钝化层。 如果除去退火后剩余硅层中的全部或部分硅,则可将厚金属硅化物层暴露于氧化环境以进行自钝化。 在后一种情况下,纯金属在硅化物中沉淀,导致比纯硅化物线更好的导电性的线,这对于互连是非常需要的。