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1. 发明授权

US4369072A Method for forming IGFET devices having improved drain voltage characteristics 失效
标题翻译：用于形成具有改善的漏极电压特性的IGFET器件的方法
公开(公告)号：US4369072A
公开(公告)日：1983-01-18
申请号：US227567
申请日：1981-01-22
申请人： Paul E. Bakeman, Jr. , Andres G. Fortino , Henry J. Geipel, Jr. , Jeffrey P. Kasold , Robert M. Quinn
发明人： Paul E. Bakeman, Jr. , Andres G. Fortino , Henry J. Geipel, Jr. , Jeffrey P. Kasold , Robert M. Quinn
IPC分类号： H01L21/265 , H01L21/336 , H01L29/08 , H01L29/78 , H01L21/263 , H01L21/22 , H01L7/00
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/0847 , H01L29/7836
摘要： A method of providing less than one micron p-n junction regions for IGFET devices in which a high concentration of arsenic is implanted so that its peak lies near the surface of a semiconductor substrate. Phosphorus is also implanted with an energy to provide a maximum concentration below that of the arsenic and of a magnitude at least one order of magnitude less than that of arsenic. An oxidation/anneal step thermally diffuses the implanted ions to form a junction less than one micron in thickness.
摘要翻译：为IGFET器件提供小于1微米的p-n结区域的方法，其中注入高浓度的砷，使得其峰位于半导体衬底的表面附近。磷也被植入能量以提供低于砷的最大浓度，并且其量比砷的至少一个数量级。氧化/退火步骤热扩散注入的离子以形成厚度小于1微米的结。

2. 发明授权

US4622573A CMOS contacting structure having degeneratively doped regions for the prevention of latch-up 失效
标题翻译： CMOS接触结构具有退化掺杂区域，以防止闩锁
公开(公告)号：US4622573A
公开(公告)日：1986-11-11
申请号：US831098
申请日：1986-02-18
申请人： Paul E. Bakeman, Jr. , Henry J. Geipel, Jr.
发明人： Paul E. Bakeman, Jr. , Henry J. Geipel, Jr.
IPC分类号： H01L27/092 , H01L29/08 , H01L29/45 , H01L29/78 , H01L29/88
CPC分类号： H01L29/456 , H01L27/0921 , H01L29/0847
摘要： A contact structure suitable for use in a CMOS device to prevent or suppress the latch-up phenomenon in the device. It uses two degeneratively doped regions of different conductivity type with a tunnel injecting interface therebetween and a conductive segment contiguous to one of the two regions. Using such a structure as the source of an FET in a CMOS arrangement causes the emitter area and the base spreading resistance of the corresponding parasitic bipolar transistor to be reduced. This in turn causes the current gain of the parasitic transistor to decrease and the latch-up phenomenon to be prevented or suppressed.
摘要翻译：适用于CMOS器件的接触结构，以防止或抑制器件中的闭锁现象。它使用具有不同导电类型的两个退化掺杂区域，其间具有隧道注入界面和与两个区域之一相邻的导电段。使用CMOS布置中的FET的源极这样的结构使得相应的寄生双极晶体管的发射极面积和基极扩展电阻降低。这又导致寄生晶体管的电流增益减小，并且可以防止或抑制闩锁现象。

3. 发明授权

US4506436A Method for increasing the radiation resistance of charge storage semiconductor devices 失效
标题翻译：提高电荷存储半导体器件的辐射电阻的方法
公开(公告)号：US4506436A
公开(公告)日：1985-03-26
申请号：US333230
申请日：1981-12-21
申请人： Paul E. Bakeman, Jr. , Robert M. Quinn
发明人： Paul E. Bakeman, Jr. , Robert M. Quinn
IPC分类号： H01L27/10 , H01L21/265 , H01L21/336 , H01L21/822 , H01L21/8242 , H01L23/556 , H01L27/04 , H01L27/08 , H01L27/108 , H01L29/78 , H01L27/02
CPC分类号： H01L23/556 , H01L27/108 , H01L2924/0002 , Y10S257/906 , Y10S438/953
摘要： A method for reducing the susceptibility of integrated circuit dynamic memory devices to environmentally produced radiation, such as alpha particles, in which a buried layer, having a majority carrier concentration substantially equal to or greater than the concentration of free carriers generated by the radiation and being between one and four orders of magnitude greater concentration than that of the semiconductor substrate, is ion implanted within a few microns of the substrate surface after at least one major high temperature processing step in the manufacturing process has been completed.
摘要翻译：一种用于降低集成电路动态存储器件对环境产生的辐射（例如α粒子）的敏感性的方法，其中掩埋层具有基本上等于或大于辐射产生的自由载流子浓度的多数载流子浓度，比半导体衬底的浓度高一到四个数量级，在制造过程中的至少一个主要的高温处理步骤完成之后离子注入到衬底表面的几微米内。

4. 发明授权

US5635285A Method and system for controlling the relative size of images formed in light-sensitive media 失效
标题翻译：用于控制在光敏介质中形成的图像的相对尺寸的方法和系统
公开(公告)号：US5635285A
公开(公告)日：1997-06-03
申请号：US487368
申请日：1995-06-07
申请人： Paul E. Bakeman, Jr. , Albert S. Bergendahl
发明人： Paul E. Bakeman, Jr. , Albert S. Bergendahl
IPC分类号： G03F1/00 , G03F7/20 , B32B3/00
CPC分类号： G03F7/70558 , G03F7/20 , G03F7/2002 , G03F7/70308 , G03F7/70333 , G03F7/70466 , Y10S428/929 , Y10T428/24628 , Y10T428/24669 , Y10T428/24802 , Y10T428/249921 , Y10T428/31504
摘要： A method of exposing a radiation-sensitive medium through a mask and using an imaging system having a given depth of focus to control for pattern dependent distortion. The steps comprise: providing the radiation-sensitive medium within the depth of focus of the imaging system; providing radiation to the radiation-sensitive medium through the mask; providing the radiation-sensitive medium fully outside the depth of focus of the imaging system; and providing radiation to the radiation-sensitive medium through the mask. Corrections are automatically made by providing the radiation-sensitive medium fully outside the depth of focus of the imaging system, since in that regime the mask operates as a grey-scale mask, with the amount of light passing through any region of the mask dependent on the transmission of the masking pattern in that region.
摘要翻译：一种通过掩模曝光辐射敏感介质并使用具有给定焦深的成像系统来控制图形相关失真的方法。这些步骤包括：在成像系统的焦点深度内提供辐射敏感介质; 通过掩模向辐射敏感介质提供辐射; 将辐射敏感介质完全放置在成像系统的焦点深度之外; 并通过掩模向辐射敏感介质提供辐射。通过将辐射敏感介质完全设置在成像系统的焦深之外自动进行校正，因为在该状态下，掩模作为灰度掩模进行操作，其中通过掩模的任何区域的光量取决于在该区域中的掩模图案的传输。

5. 发明授权

US5556802A Method of making corrugated vertical stack capacitor (CVSTC) 失效
标题翻译：波纹垂直叠层电容器（CVSTC）制作方法
公开(公告)号：US5556802A
公开(公告)日：1996-09-17
申请号：US486630
申请日：1995-06-07
申请人： Paul E. Bakeman, Jr. , Bomy A. Chen , John E. Cronin , Steven J. Holmes , Hing Wong
发明人： Paul E. Bakeman, Jr. , Bomy A. Chen , John E. Cronin , Steven J. Holmes , Hing Wong
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90 , Y10S438/949
摘要： A method for forming a capacitor on a substrate having a contact below a top layer including the steps of:Spinning on a layer of photoresist material. Exposing the photoresist to light to establish a standing wave pattern to fix prominences of photoresist separated by separation areas. Each prominence extends a prominence height from the top layer to a top. Developing the photoresist to fix an erose face on each prominence, each face extending from the top layer to the top. Depositing a first oxide intermediate prominences to effect accumulation of the first oxide to an oxide height at least equal to the prominence height. Etching the first oxide to expose each top. Dissolving the photoresist to uncover oxide mandrels. Each mandrel extends a mandrel height from the top layer to a mandrel top; each mandrel has an erose mandrel face intermediate the top layer and the mandrel top. Etching the top layer to expose the contact. Depositing a first silicon material over selected mandrels, the top layer, and the contact intermediate the selected mandrels. Depositing photoresist over the first silicon. Etching the photoresist and the first silicon to the mandrel height to establish a node capacitor electrode. Stripping the photoresist remaining. Stripping the first oxide. Depositing a second oxide over the node electrode to establish a capacitor dielectric layer. Depositing a second silicon material over the dielectric layer to establish a plate capacitor electrode.
摘要翻译：一种在具有在顶层之下具有接触的基底上形成电容器的方法，包括以下步骤：在光致抗蚀剂材料层上旋转。将光致抗蚀剂曝光以建立驻波图案以固定由分离区域分离的光致抗蚀剂的突出部分。每个突出部分从顶层延伸到顶部。显影光致抗蚀剂以在每个突起处固定一个正面，每个面从顶层延伸到顶部。沉积第一氧化物中间体以使第一氧化物积累至至少等于突出高度的氧化物高度。蚀刻第一氧化物以暴露每个顶部。溶解光致抗蚀剂以露出氧化物心轴。每个心轴将心轴高度从顶层延伸到心轴顶部; 每个心轴具有在顶层和心轴顶部之间的中心轴。蚀刻顶层以暴露接触。将第一硅材料沉积在选定的心轴，顶层和选定的心轴之间的接触之上。在第一硅上沉积光致抗蚀剂。将光致抗蚀剂和第一硅蚀刻到心轴高度以建立节点电容器电极。剥离残留的光致抗蚀剂。剥去第一氧化物。在节点电极上沉积第二氧化物以建立电容器介电层。在电介质层上沉积第二硅材料以建立平板电容器电极。

6. 发明授权

US08569896B2 Active area bonding compatible high current structures 有权
公开(公告)号：US08569896B2
公开(公告)日：2013-10-29
申请号：US13532843
申请日：2012-06-26
申请人： John T. Gasner , Michael D. Church , Sameer D. Parab , Paul E. Bakeman, Jr. , David A. Decrosta , Robert Lomenick , Chris A. McCarty
发明人： John T. Gasner , Michael D. Church , Sameer D. Parab , Paul E. Bakeman, Jr. , David A. Decrosta , Robert Lomenick , Chris A. McCarty
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/76801 , H01L21/32051 , H01L21/76829 , H01L21/76841 , H01L21/7685 , H01L21/76886 , H01L23/528 , H01L23/53295 , H01L24/03 , H01L24/05 , H01L24/48 , H01L24/81 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/04941 , H01L2924/14 , H01L2224/45099
摘要： A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

7. 发明授权

US5480748A Protection of aluminum metallization against chemical attack during photoresist development 失效
标题翻译：在光刻胶显影过程中保护铝金属化免遭化学侵蚀
公开(公告)号：US5480748A
公开(公告)日：1996-01-02
申请号：US233679
申请日：1994-04-26
申请人： Paul E. Bakeman, Jr. , Hyun K. Lee , Stephen E. Luce
发明人： Paul E. Bakeman, Jr. , Hyun K. Lee , Stephen E. Luce
IPC分类号： G03F7/11 , H01L21/02 , H01L21/321 , H01L21/3213 , G03F7/16
CPC分类号： H01L21/02071 , G03F7/11 , H01L21/321 , Y10S148/015 , Y10S438/958
摘要： A conductive layer in a semiconductor device is protected against chemical attack by a photoresist developer by forming a protective film overlying the conductive layer. The protective film is formed using a chemical reaction that occurs through defects in a passivation layer that was previously formed overlying the conductive layer. The chemical reaction substantially occurs at the surface of the conductive layer and chemically converts portions thereof in forming the protective film. Preferably, the conductive layer is aluminum or an alloy thereof containing copper and/or silicon, and the protective film is aluminum oxide formed on the aluminum layer to protect it from corrosion by tetramethyl ammonium hydroxide (TMAH). The passivation layer is TiN, and the chemical reaction used is oxidation of the aluminum layer through defects in the overlying TiN layer by placing in an ozone asher.
摘要翻译：通过形成覆盖导电层的保护膜，保护半导体器件中的导电层免受光致抗蚀剂显影剂的化学侵蚀。使用通过先前形成在导电层上的钝化层中的缺陷发生的化学反应形成保护膜。化学反应基本发生在导电层的表面，并在形成保护膜时化学转化其部分。优选地，导电层是铝或其含有铜和/或硅的合金，并且保护膜是在铝层上形成的氧化铝，以保护其免受四甲基氢氧化铵（TMAH）的腐蚀。钝化层是TiN，所用的化学反应是通过放置在臭氧灰中，通过上覆TiN层中的缺陷来氧化铝层。

8. 发明授权

US07795130B2 Active area bonding compatible high current structures 有权
标题翻译：有源区粘合兼容高电流结构
公开(公告)号：US07795130B2
公开(公告)日：2010-09-14
申请号：US11737392
申请日：2007-04-19
申请人： John T. Gasner , Michael D. Church , Sameer D. Parab , Paul E. Bakeman, Jr. , David A. Decrosta , Robert Lomenick , Chris A. McCarty
发明人： John T. Gasner , Michael D. Church , Sameer D. Parab , Paul E. Bakeman, Jr. , David A. Decrosta , Robert Lomenick , Chris A. McCarty
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L23/528 , H01L23/53295 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05166 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/01007 , H01L2224/45099
摘要： A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.
摘要翻译：提供一种形成半导体结构的方法。一种方法包括在衬底和接合衬垫之间形成器件区域。在接合焊盘和具有间隙的器件区域之间形成导体。使用比导体硬的绝缘材料填充间隙，以形成延伸穿过导体的相对硬的材料的支柱，并在导体和接合垫之间形成绝缘材料的绝缘层。

9. 发明授权

US07005369B2 Active area bonding compatible high current structures 有权
标题翻译：有源区粘合兼容高电流结构
公开(公告)号：US07005369B2
公开(公告)日：2006-02-28
申请号：US10698184
申请日：2003-10-31
申请人： John T. Gasner , Michael D. Church , Sameer D. Parab , Paul E. Bakeman, Jr. , David A. Decrosta , Robert L. Lomenick , Chris A. McCarty
发明人： John T. Gasner , Michael D. Church , Sameer D. Parab , Paul E. Bakeman, Jr. , David A. Decrosta , Robert L. Lomenick , Chris A. McCarty
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L23/528 , H01L23/53295 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05166 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/01007 , H01L2224/45099
摘要： An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.
摘要翻译：一个集成电路，具有一个接合焊盘下的电路。在一个实施例中，集成电路包括衬底，顶部导电层，一个或多个中间导电层，绝缘材料和器件层。顶部导电层具有至少一个焊盘和相对刚性材料的子层。一个或多个中间导电层形成在顶部导电层和基底之间。绝缘材料层分离导电层。此外，绝缘材料层的一层相对较硬，并且位于顶部导电层和最靠近顶部导电层的中间导电层之间。器件形成在集成电路中。此外，至少最靠近顶部导电层的中间导电层适用于接合焊盘下的选择器件的功能互连。

10. 发明授权

US5347153A Short channel transistors 失效
标题翻译：短沟道晶体管
公开(公告)号：US5347153A
公开(公告)日：1994-09-13
申请号：US124521
申请日：1993-09-20
申请人： Paul E. Bakeman, Jr.
发明人： Paul E. Bakeman, Jr.
IPC分类号： H01L29/78 , H01L21/336 , H01L29/10 , H01L27/01 , H01L29/00
CPC分类号： H01L29/66659 , H01L29/1083 , H01L29/1087
摘要： An improved short channel field effect transistor is provided which includes a semiconductor substrate having a given type dopant with source and drain electrodes, one of the electrodes having a diffusion of the type of dopant opposite to that of the given type dopant, a channel disposed between the source and drain electrodes, a region having the same type dopant as that of the substrate and aligned with the diffusion at the diffusion-channel interface, the region having sufficient dopant to prevent penetration of the depletion region generated by the diffusion into the substrate or at least to significantly limit the electric field which results from the junction between the diffusion and the substrate and an electrically conductive contact made with the diffusion, which may be, e.g., connected to a substantially constant bias or supply voltage source.
摘要翻译：提供了一种改进的短沟道场效应晶体管，其包括具有给定类型掺杂剂的源极和漏极的半导体衬底，其中一个电极具有与给定类型掺杂剂相反的掺杂类型的扩散，源电极和漏电极，具有与衬底相同类型掺杂剂并与扩散 - 沟道界面处的扩散相对准的区域，该区域具有足够的掺杂剂以防止由扩散产生的耗尽区穿透到衬底中，或至少显着地限制由扩散和衬底之间的接合产生的电场以及由扩散制成的导电触点，其可以例如连接到基本上恒定的偏压或电源电压源。

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