专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050228910A1 Method for providing an area optimized binary orthogonality checker 失效
标题翻译：提供区域优化二进制正交检验器的方法
公开(公告)号：US20050228910A1
公开(公告)日：2005-10-13
申请号：US10817279
申请日：2004-04-02
申请人： Patrick Meaney , Alan Wagstaff
发明人： Patrick Meaney , Alan Wagstaff
IPC分类号： G03C1/52 , G06F17/50
CPC分类号： G06F17/5045
摘要： A method for minimizing the area of a binary orthogonality checker implemented in static CMOS circuits for minimizing the gate count and area needed for checker implementation. The method is adaptable to various libraries of logical gates to implement the circuit and the area for each gate in the library. The optimal mix of hierarchical levels and stages is determined such that the orthogonality checker achieves the minimized circuit area. An orthogonality checker is employed in a scalable selector system for controlling data transfers and routing in a data processing system to allow. Combining orthogonality checking with existing selector hierarchically allows for the maximum reuse of circuits, signals, and proximity; thus potentially reducing wiring as well. Multiple hierarchical checks are used in favor of one large. This structure is extended to multiple hierarchical levels and works with orthogonality checks of any size or implementation. The invention also determines the optimal hierarchical structure for a given technology library and a given number of inputs to check. It can also be used within a flat hierarchy or macro as a technique to reduce circuits.
摘要翻译：一种用于最小化在静态CMOS电路中实现的二进制正交检验器的面积的方法，用于最小化检验器实现所需的门数和面积。该方法适用于逻辑门的各种库，以实现库中每个门的电路和区域。确定层次级别和级别的最佳组合，使得正交检验器实现最小化的电路面积。在可扩展选择器系统中采用正交检验器，用于在数据处理系统中控制数据传输和路由以允许。将正交检查与现有选择器分层组合允许电路，信号和接近度的最大重用; 从而潜在地减少布线。使用多层次检查有利于一个大型。该结构扩展到多个层次级别，并且可以与任何大小或实现的正交性检查一起工作。本发明还确定给定技术库的最优层次结构以及给定数量的输入以进行检查。它也可以在平面层级或宏中用作减少电路的技术。

2. 发明申请

US20050149802A1 Multi nodal computer system and method for handling check stops in the multi nodal computer system 失效
标题翻译：多节点计算机系统和多节点计算机系统中检查停止处理方法
公开(公告)号：US20050149802A1
公开(公告)日：2005-07-07
申请号：US11013728
申请日：2004-12-16
申请人： Karin Rebmann , Dietmar Schmunkamp , Tobias Webel , Thomas Gilbert , Timothy McNamara , Patrick Meaney
发明人： Karin Rebmann , Dietmar Schmunkamp , Tobias Webel , Thomas Gilbert , Timothy McNamara , Patrick Meaney
IPC分类号： G01R31/28
CPC分类号： G06F11/0793 , G06F9/544 , G06F11/0709 , Y10S707/99931 , Y10S707/99939 , Y10S707/99943
摘要： The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.
摘要翻译：本发明提供了一种新的多节点计算机系统，其包括不同类型的芯片所驻留的多个节点。新的多节点计算机系统的特征在于每个节点有一个时钟芯片，每个时钟芯片仅控制驻留在该节点上的芯片，所述芯片适合于在发生故障的情况下向相关联的时钟芯片发送检查停止请求。新的检查停止处理方法的特征在于，根据检查停止请求的来源，接收到检查停止请求的时钟芯片启动系统检查停止，节点检查或芯片检查停止。

3. 发明授权

US08095837B2 Method and apparatus for improving random pattern testing of logic structures 有权
标题翻译：改进逻辑结构随机模式测试的方法和装置
公开(公告)号：US08095837B2
公开(公告)日：2012-01-10
申请号：US12051744
申请日：2008-03-19
申请人： Mary P. Kusko , Barry W. Krumm , Patrick Meaney , Bryan J. Robbins
发明人： Mary P. Kusko , Barry W. Krumm , Patrick Meaney , Bryan J. Robbins
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318385
摘要： A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves in a functional manner during random testing, and generating patterns to exercise the modified logic structure.
摘要翻译：一种用于随机测试逻辑结构的测试方法和设备。该方法包括识别和分析在随机测试期间要覆盖的逻辑结构的功能行为，修改逻辑结构，使得逻辑结构在随机测试期间以功能方式行为，以及生成用于执行修改的逻辑结构的模式。

4. 发明申请

US20060242510A1 Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing 有权
公开(公告)号：US20060242510A1
公开(公告)日：2006-10-26
申请号：US11336082
申请日：2006-01-20
申请人： Patrick Meaney , Timothy McNamara , Bryan Mechtly
发明人： Patrick Meaney , Timothy McNamara , Bryan Mechtly
IPC分类号： G01R31/28
CPC分类号： G11C29/78 , G01R31/318541
摘要： An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) testing. The method makes use of programmable fuses which contain Level Sensitive Scan Design (LSSD) latches which also have a system port. The system port allows for simpler reading of the fuses as well as for the dynamic updates of the programmable fuses for wordline and other repairs.

5. 发明申请

US20060179394A1 Method and apparatus for collecting failure information on error correction code (ECC) protected data 有权
标题翻译：收集有关纠错码（ECC）保护数据的故障信息的方法和装置
公开(公告)号：US20060179394A1
公开(公告)日：2006-08-10
申请号：US11054575
申请日：2005-02-09
申请人： Arthur O'Neill , Patrick Meaney
发明人： Arthur O'Neill , Patrick Meaney
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.
摘要翻译：纠错码（ECC）调试的方法和手段可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。

6. 发明申请

US20060031796A1 Method for swapping circuits in a metal-only engineering change 失效
标题翻译：仅在金属工程变更中交换电路的方法
公开(公告)号：US20060031796A1
公开(公告)日：2006-02-09
申请号：US10894664
申请日：2004-07-20
申请人： Patrick Meaney
发明人： Patrick Meaney
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045 , G06F2217/64
摘要： A method is disclosed for improving design criteria and importantly timing criteria following a metal-only engineering change. The method involves making initial logical changes involving new books (gate-level, filler-cell circuits, called ‘eco books’), running placement and routing with the new books, and timing the resulting logic. If there are timing violations, existing, non-filler books which are in close proximity are considered for swapping with the eco books. The book swaps are all done with wire connections only (i.e. the book placements are not affected). This way, critical paths and non-critical paths can be traded-off to achieve a faster design, even though books are not allowed to be moved. Some simple algorithms are discussed; however, there are many heuristic and analytic algorithms that can be applied in choosing swaps, based on the needs of the particular design.
摘要翻译：公开了一种在金属工程变更之后改进设计标准和重要的时间标准的方法。该方法包括进行新书（门级，填充单元电路，称为“生态书”）的初始逻辑更改，使用新书运行布局和路由，以及计算结果逻辑。如果存在时间违规，则认为与生态书籍进行交换的现有非填充书。书籍交换全部仅通过电线连接完成（即图书布置不受影响）。这样，关键路径和非关键路径可以被交换，以实现更快的设计，即使书籍不被允许移动。讨论了一些简单的算法; 然而，根据特定设计的需要，有许多启发式和分析算法可以应用于选择交换。

7. 发明申请

US20090240995A1 METHOD AND APPARATUS FOR IMPROVING RANDOM PATTERN TESTING OF LOGIC STRUCTURES 有权
标题翻译：改进逻辑结构随机模式测试的方法和装置
公开(公告)号：US20090240995A1
公开(公告)日：2009-09-24
申请号：US12051744
申请日：2008-03-19
申请人： Mary P. Kusko , Barry W. Krumm , Patrick Meaney , Bryan J. Robbins
发明人： Mary P. Kusko , Barry W. Krumm , Patrick Meaney , Bryan J. Robbins
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/318385
摘要： A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves in a functional manner during random testing, and generating patterns to exercise the modified logic structure.
摘要翻译：一种用于随机测试逻辑结构的测试方法和设备。该方法包括识别和分析在随机测试期间要覆盖的逻辑结构的功能行为，修改逻辑结构，使得逻辑结构在随机测试期间以功能方式行为，以及生成用于执行修改的逻辑结构的模式。

8. 发明申请

US20060203578A1 Apparatus and method for self-correcting cache using line delete, data logging, and fuse repair correction 有权
标题翻译：使用行删除，数据记录和保险丝修复校正来自动校正缓存的装置和方法
公开(公告)号：US20060203578A1
公开(公告)日：2006-09-14
申请号：US11079816
申请日：2005-03-14
申请人： Patrick Meaney , William Huott , Thomas Knips , David Lund , Bryan Mechtly , Pradip Patel
发明人： Patrick Meaney , William Huott , Thomas Knips , David Lund , Bryan Mechtly , Pradip Patel
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C11/41 , G11C15/00 , G11C29/4401 , G11C29/789 , G11C2029/0407 , G11C2029/1208
摘要： An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are defective, identify corresponding fuse repair values, proactively call home if spare fuses are not available, schedule soft fuse repairs for the next system restart, schedule line deletes at the next restart, store delete and fuse repairs in a table (tagged with electronic serial id, timestamp of delete or ABIST fail event, address, and type of failure) and proactively call home if there were any missed deletes that were not logged. Fuse information can also be more permanently stored into hardware electronic fuses and/or EPROMs. During a restart, previous repairs are able to be applied to the machine so that ABIST will run successfully and previous deletes to be maintained with checking to allow some ABIST failures which are protected by the line deletes to pass.
摘要翻译：一种用于保护计算机系统免受阵列可靠性故障的装置和方法使用阵列内置自检逻辑以及代码和硬件来删除有缺陷的高速缓存行或集合，识别相应的保险丝修复值，如果备用保险丝为主动式，则主动呼叫家庭不可用，为下一次重新启动计划软保险丝修复，下次重新启动时计划行删除，在表中存储删除和保险丝修复（标记为电子序列号，删除时间戳或ABIST失败事件，地址和故障类型），并且如果有任何未被记录的遗漏的删除事件，则主动呼叫回家。保险丝信息也可以更加永久地存储在硬件电子保险丝和/或EPROM中。在重新启动期间，以前的修复可以应用于机器，以便ABIST将成功运行，以前的删除将通过检查进行维护，以允许由删除行保护的一些ABIST故障通过。

9. 发明申请

US20050268187A1 Method for deferred data collection in a clock running system 有权
标题翻译：时钟运行系统中延迟数据采集的方法
公开(公告)号：US20050268187A1
公开(公告)日：2005-12-01
申请号：US10855047
申请日：2004-05-27
申请人： Patrick Meaney , Kurt Grassmann , Oliver Marquardt , Scott Swaney
发明人： Patrick Meaney , Kurt Grassmann , Oliver Marquardt , Scott Swaney
IPC分类号： G06F11/00 , G08C25/00 , G11C29/00 , H03M13/00 , H04L1/00
CPC分类号： G06F11/3636 , G06F11/0724 , G06F11/0772 , G06F11/0778
摘要： A method for deferred logging of machine data following an error or event in order to capture critical information for that error or event treats the data as persistent and it does not get logged until a disruption occurs to the system (e.g. system reset, restart, deactivation, or powered-down). This way, important debug data can be held in the hardware or software, without a need for complicated hardware and code for logging this debug data. Methods are also disclosed for setting a switch to indicate deferred logging is required, referencing the log data with the original event information, calling home with the debug data, resetting the deferred logging switch, setting the deferred logging switch manually, viewing whether the switch is already set, and supporting different kinds of switches.
摘要翻译：在错误或事件之后延迟记录机器数据以便捕获该错误或事件的关键信息的方法将数据视为持久性，并且在系统发生中断之前不会记录数据（例如系统复位，重新启动，停用，或掉电）。这样，重要的调试数据可以在硬件或软件中保存，而无需复杂的硬件和代码来记录调试数据。还公开了设置交换机以指示延迟日志记录的方法，参考具有原始事件信息的日志数据，使用调试数据调用主机，重新设置延迟记录交换机，手动设置延迟日志记录交换机，查看交换机是否已经设置，并支持不同种类的交换机。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式