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1. 发明授权

US06766429B1 Low cost and high RAS mirrored memory 失效
标题翻译：低成本和高RAS镜像记忆
公开(公告)号：US06766429B1
公开(公告)日：2004-07-20
申请号：US09652752
申请日：2000-08-31
申请人： Patrick Maurice Bland , Thomas Basil Smith, III , Robert Brett Tremaine , Michael Edward Wazlowski
发明人： Patrick Maurice Bland , Thomas Basil Smith, III , Robert Brett Tremaine , Michael Edward Wazlowski
IPC分类号： G06F1200
CPC分类号： G06F11/1666 , G06F11/20 , G06F12/023 , G06F12/0292 , G06F2212/401
摘要： An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank. After a memory bank is identified as faulty, the memory controller precludes further read access to the bank, permitting replacement without interruption to the application or operating system software operation.
摘要翻译：具有存储器压缩的数据处理系统的结构，方法和装置以及形成单个统一存储器的两个公共存储器或能够在存在硬件故障或冗余“双工”计算机维护中断时能够连续操作的双存储器系统，而不需要复制存储器件的成本。存储器控制器采用硬件存储器压缩以将存储器需求减少一半，这补偿了冗余存储器所需的存储器的倍增。存储器控制器采用错误检测和校正码，用于在读取访问期间检测存储子系统故障。在检测到故障时，硬件自动将读访问重新发送到逻辑上与故障库相同的单独的存储体。在存储器被识别为故障之后，存储器控制器排除对存储体的进一步读取访问，允许更换而不中断应用程序或操作系统软件操作。

2. 发明授权

US07287138B2 Low cost and high RAS mirrored memory 失效
标题翻译：低成本和高RAS镜像记忆
公开(公告)号：US07287138B2
公开(公告)日：2007-10-23
申请号：US10859826
申请日：2004-06-03
申请人： Patrick Maurice Bland , Thomas Basil Smith, III , Robert Brett Tremaine , Michael Edward Wazlowski
发明人： Patrick Maurice Bland , Thomas Basil Smith, III , Robert Brett Tremaine , Michael Edward Wazlowski
IPC分类号： G06F12/00
CPC分类号： G06F11/1666 , G06F11/20 , G06F12/023 , G06F12/0292 , G06F2212/401
摘要： An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank. After a memory bank is identified as faulty, the memory controller precludes further read access to the bank, permitting replacement without interruption to the application or operating system software operation.
摘要翻译：具有存储器压缩的数据处理系统的结构，方法和装置以及形成单个统一存储器的两个公共存储器或能够在存在硬件故障或冗余“双工”计算机维护中断时能够连续操作的双存储器系统，而不需要复制存储器件的成本。存储器控制器采用硬件存储器压缩以将存储器需求减少一半，这补偿了冗余存储器所需的存储器的倍增。存储器控制器采用错误检测和校正码，用于在读取访问期间检测存储子系统故障。在检测到故障时，硬件自动将读访问重新发送到逻辑上与故障库相同的单独的存储体。在存储器被识别为故障之后，存储器控制器排除对存储体的进一步读取访问，允许更换而不中断应用程序或操作系统软件操作。

3. 发明授权

US06339813B1 Memory system for permitting simultaneous processor access to a cache line and sub-cache line sectors fill and writeback to a system memory 失效
标题翻译：用于允许同时处理器访问高速缓存行和子高速缓存行扇区的存储器系统填充和回写到系统存储器
公开(公告)号：US06339813B1
公开(公告)日：2002-01-15
申请号：US09480702
申请日：2000-01-07
申请人： Thomas Basil Smith, III , Robert Brett Tremaine
发明人： Thomas Basil Smith, III , Robert Brett Tremaine
IPC分类号： G06F1314
CPC分类号： G06F12/0859
摘要： In a cache memory system, a mechanism enabling two logical cache lines to coexist within the same physical cache line, during line fill and replacement, thus minimizing the likelihood of stalling accesses to the cache while the line is being filled or replaced. A control mechanism governs access to the cache line and tracks which sub-cache line units contain old or new data, or are empty during the fill/replacement procedure. The control mechanism thus maintains a sub-cache line state for the purpose of permitting a processor to gain access to a portion of the cache line before it is completely filled or replaced.
摘要翻译：在高速缓冲存储器系统中，在行填充和替换期间，能够使两个逻辑高速缓存行在同一物理高速缓存行内共存的机制，从而最小化在线被填充或替换时停止对高速缓存的访问的可能性。控制机制控制对高速缓存行的访问，并跟踪哪些子高速缓存行单元包含旧数据或新数据，或者在填充/替换过程期间为空。因此，控制机制保持子高速缓存线路状态，以便允许处理器在完全填充或替换之前获得对高速缓存行的一部分的访问。

4. 发明授权

US08490065B2 Method and apparatus for software-assisted data cache and prefetch control 有权
标题翻译：用于软件辅助数据缓存和预取控制的方法和装置
公开(公告)号：US08490065B2
公开(公告)日：2013-07-16
申请号：US11250054
申请日：2005-10-13
申请人： Roch Archambault , Yaoqing Gao , Francis Patrick O'Connell , Robert Brett Tremaine , Michael Edward Wazlowski , Steven Wayne White , Lixin Zhang
发明人： Roch Archambault , Yaoqing Gao , Francis Patrick O'Connell , Robert Brett Tremaine , Michael Edward Wazlowski , Steven Wayne White , Lixin Zhang
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F9/3879 , G06F8/4442 , G06F9/30047 , G06F9/3455 , G06F12/0862 , G06F2212/6028
摘要： The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.
摘要翻译：本发明提供了一种用于编译用于管理高速缓存系统的指令的计算机实现的方法，装置和计算机可用程序代码。分析循环结构以识别指令中的缓存和预取条件的数据使用特征以形成识别的预取条件。基于数据使用特性和识别的预取条件将一组控制指令插入到指令中以形成多个修改的指令。编译多组修改指令的集合以生成用于执行的代码以形成编译指令。编译指令中的一组控制指令形成高速缓存管理策略以在执行编译指令期间控制存储器系统中数据的移动。

5. 发明授权

US08949837B2 Assist thread for injecting cache memory in a microprocessor 有权
标题翻译：协助在微处理器中注入高速缓存的线程
公开(公告)号：US08949837B2
公开(公告)日：2015-02-03
申请号：US13434423
申请日：2012-03-29
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F12/00 , G06F9/38 , G06F12/08 , G06F9/48
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

6. 发明授权

US07934061B2 Methods and arrangements to manage on-chip memory to reduce memory latency 有权
标题翻译：管理片上存储器以减少内存延迟的方法和安排
公开(公告)号：US07934061B2
公开(公告)日：2011-04-26
申请号：US12145034
申请日：2008-06-24
申请人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
发明人： Dilma Menezes da Silva , Elmootazbellah Nabil Elnozahy , Orran Yaakov Krieger , Hazim Shafi , Xiaowei Shen , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F12/00 , G06F13/00 , G06F3/00
CPC分类号： G06F12/08 , G06F12/0893 , G06F2212/251 , G06F2212/253
摘要： Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
摘要翻译：考虑通过操作系统提供对软件应用（OCM）的控制的措施来减少处理器所看到的存储器延迟的方法，系统和媒体。许多实施例允许OCM的一部分由软件应用程序通过应用程序接口（API）和由硬件管理的部分来管理。因此，软件应用程序可以提供关于地址范围的指导，以保持靠近处理器，以减少在依赖于缓存控制器策略时通常遇到的不必要的延迟。几个实施例利用处理器内部或处理器节点上的存储器，因此用于该技术的存储器块被称为OCM。

7. 发明授权

US08433950B2 System to determine fault tolerance in an integrated circuit and associated methods 失效
标题翻译：确定集成电路中容错的系统及相关方法
公开(公告)号：US08433950B2
公开(公告)日：2013-04-30
申请号：US12405858
申请日：2009-03-17
申请人： Mark A. Check , Andrew R. Ranck , Robert Brett Tremaine
发明人： Mark A. Check , Andrew R. Ranck , Robert Brett Tremaine
IPC分类号： G06F11/00
CPC分类号： G06F11/1048
摘要： A system to determine fault tolerance in an integrated circuit may include a programmable logic device carried by the integrated circuit. The system may also include a configurable memory carried by the programmable logic device to control the function and/or connection of a portion of the programmable logic device. The system may further include user logic carried by said programmable logic device and in communication with a user and/or the configurable memory. The user logic may identify corrupted data in the configurable memory based upon changing user requirements.
摘要翻译：用于确定集成电路中的容错的系统可以包括由集成电路承载的可编程逻辑器件。该系统还可以包括可编程逻辑器件承载的可配置存储器，以控制可编程逻辑器件的一部分的功能和/或连接。该系统还可以包括由所述可编程逻辑设备携带并与用户和/或可配置存储器通信的用户逻辑。用户逻辑可以基于改变的用户需求来识别可配置存储器中的损坏的数据。

8. 发明授权

US06658548B1 System and method in a data processing system for extracting data from a protected region of memory 有权
标题翻译：用于从存储器的受保护区域提取数据的数据处理系统中的系统和方法
公开(公告)号：US06658548B1
公开(公告)日：2003-12-02
申请号：US09480760
申请日：2000-01-10
申请人： Sumeet Kochar , Mary Joan McHugh , James Gerard Palte , Dan Edward Poff , Robert Saccone, Jr. , Charles Otto Schulz , Robert Brett Tremaine
发明人： Sumeet Kochar , Mary Joan McHugh , James Gerard Palte , Dan Edward Poff , Robert Saccone, Jr. , Charles Otto Schulz , Robert Brett Tremaine
IPC分类号： G06F1200
CPC分类号： G06F12/10 , G06F12/145 , G06F2212/401
摘要： A system and method for extracting data from a protected region of memory loads at least a first part of extraction code into physical memory and, thereafter, activates a memory mapping facility that maps a real memory onto the physical memory and prevents programs from accessing a protected memory region of the physical memory. At least a second part of the extraction code is then loaded into the virtual memory utilizing the memory mapping facility. The extraction code is then executed to deactivate the memory mapping facility and to copy data from the protected memory region to a second physical memory region, such that reactivating the memory mapping facility will cause a real memory region to be mapped onto the second physical memory region.
摘要翻译：用于从存储器的受保护区域提取数据的系统和方法将至少提取代码的第一部分加载到物理存储器中，并且此后激活将真实存储器映射到物理存储器上并防止程序访问受保护的存储器物理内存的内存区域。然后使用存储器映射设备将提取码的至少第二部分加载到虚拟存储器中。然后执行提取代码以去激活存储器映射设备并将数据从受保护的存储器区域复制到第二物理存储器区域，使得重新激活存储器映射设备将使真实存储器区域映射到第二物理存储器区域。

9. 发明授权

US07962700B2 Systems and methods for reducing latency for accessing compressed memory using stratified compressed memory architectures and organization 有权
标题翻译：使用分层压缩内存架构和组织来减少访问压缩内存的延迟的系统和方法
公开(公告)号：US07962700B2
公开(公告)日：2011-06-14
申请号：US11516188
申请日：2006-09-06
申请人： Peter Anthony Franaszek , Luis Alfonso Lastras-Montano , Robert Brett Tremaine
发明人： Peter Anthony Franaszek , Luis Alfonso Lastras-Montano , Robert Brett Tremaine
IPC分类号： G06F13/12 , G06F12/00 , G06F9/26 , G06F11/00 , G09G5/00
CPC分类号： G06T1/60 , G06F12/0897 , G06F12/1081 , G06F2212/401 , G11C7/1006 , G11C2207/102
摘要： Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.
摘要翻译：提供压缩存储器系统以减少使用分层压缩存储器架构和存储器组织协议访问压缩存储器的延迟，其中压缩主存储器的区域被分配为用于存储未压缩数据项的直接存取存储器（DAM）区域。可以直观地访问DAM区域中的未压缩数据项，从而提供对主存储器的访问请求，在遇到DAM缺失时需要访问压缩存储器。

10. 发明申请

US20100241900A1 SYSTEM TO DETERMINE FAULT TOLERANCE IN AN INTEGRATED CIRCUIT AND ASSOCIATED METHODS 失效
标题翻译：确定集成电路中的故障容限和相关方法的系统
公开(公告)号：US20100241900A1
公开(公告)日：2010-09-23
申请号：US12405858
申请日：2009-03-17
申请人： Mark A. Check , Andrew R. Ranck , Robert Brett Tremaine
发明人： Mark A. Check , Andrew R. Ranck , Robert Brett Tremaine
IPC分类号： G01R31/3177 , G06F11/14 , G06F11/25
CPC分类号： G06F11/1048
摘要： A system to determine fault tolerance in an integrated circuit may include a programmable logic device carried by the integrated circuit. The system may also include a configurable memory carried by the programmable logic device to control the function and/or connection of a portion of the programmable logic device. The system may further include user logic carried by said programmable logic device and in communication with a user and/or the configurable memory. The user logic may identify corrupted data in the configurable memory based upon changing user requirements.
摘要翻译：用于确定集成电路中的容错的系统可以包括由集成电路承载的可编程逻辑器件。该系统还可以包括可编程逻辑器件承载的可配置存储器，以控制可编程逻辑器件的一部分的功能和/或连接。该系统还可以包括由所述可编程逻辑设备携带并与用户和/或可配置存储器通信的用户逻辑。用户逻辑可以基于改变的用户需求来识别可配置存储器中的损坏的数据。

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