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1. 发明授权

US07902904B2 Bias circuit scheme for improved reliability in high voltage supply with low voltage device 有权
标题翻译：偏压电路方案，用于提高低压电源的可靠性
公开(公告)号：US07902904B2
公开(公告)日：2011-03-08
申请号：US12330828
申请日：2008-12-09
申请人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
发明人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
IPC分类号： G05F1/10
CPC分类号： G05F3/16
摘要： Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.
摘要翻译：公开了一种偏置电路，其中第一电阻器连接在电源电压和反馈节点之间。电阻器连接在反馈节点和参考电源电压之间。电阻之间的连接限定了至少一个偏置电压。第二电阻器连接在反馈节点和第一漏极节点之间。第一场效应晶体管具有第一栅极节点，第一漏极节点和第一源节点。门节点连接到第一电源电压。第二场效应晶体管具有第二栅极节点，第二漏极节点和第二源节点。第二排水节点连接到第一源节点。第二栅极节点连接到偏置电压。第二源节点连接到输出信号节点。输出信号节点能够经历过冲电压。

2. 发明申请

US20100141334A1 Bias circuit scheme for improved reliability in high voltage supply with low voltage device 有权
标题翻译：偏压电路方案，用于提高低压电源的可靠性
公开(公告)号：US20100141334A1
公开(公告)日：2010-06-10
申请号：US12330828
申请日：2008-12-09
申请人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
发明人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
IPC分类号： G05F1/10
CPC分类号： G05F3/16
摘要： Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.
摘要翻译：公开了一种偏置电路，其中第一电阻器连接在电源电压和反馈节点之间。电阻器连接在反馈节点和参考电源电压之间。电阻之间的连接限定了至少一个偏置电压。第二电阻器连接在反馈节点和第一漏极节点之间。第一场效应晶体管具有第一栅极节点，第一漏极节点和第一源节点。门节点连接到第一电源电压。第二场效应晶体管具有第二栅极节点，第二漏极节点和第二源节点。第二排水节点连接到第一源节点。第二栅极节点连接到偏置电压。第二源节点连接到输出信号节点。输出信号节点能够经历过冲电压。

3. 发明申请

US20100271118A1 I/O Buffer with Low Voltage Semiconductor Devices 失效
标题翻译：带低压半导体器件的I / O缓冲器
公开(公告)号：US20100271118A1
公开(公告)日：2010-10-28
申请号：US12428556
申请日：2009-04-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
IPC分类号： G05F1/10
CPC分类号： H03K17/0822 , H03K19/018528
摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.
摘要翻译：所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。从缓冲器的工作电压产生第一和第二偏置电压。从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压缓冲。第三和第四偏置电压分别提供给第一和第二过压保护电路。

4. 发明授权

US07936209B2 I/O buffer with low voltage semiconductor devices 失效
标题翻译：具有低电压半导体器件的I / O缓冲器
公开(公告)号：US07936209B2
公开(公告)日：2011-05-03
申请号：US12428556
申请日：2009-04-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K17/0822 , H03K19/018528
摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.
摘要翻译：所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。从缓冲器的工作电压产生第一和第二偏置电压。从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压缓冲。第三和第四偏置电压分别提供给第一和第二过压保护电路。

5. 发明授权

US08536925B2 Voltage level translator circuit 有权
标题翻译：电压电平转换电路
公开(公告)号：US08536925B2
公开(公告)日：2013-09-17
申请号：US12598352
申请日：2008-12-29
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Jeffrey J. Nagy , Peter J. Nicholas
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Jeffrey J. Nagy , Peter J. Nicholas
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/0375
摘要： A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).
摘要翻译：电压转换器电路（320）包括适于接收参考第一电压源（VDD核心）的输入信号的输入级（322），适于连接到第二电压源（VDD33）的锁存器（326）至少临时存储输入信号的逻辑状态，以及耦合在输入级（322）和锁存器（326）之间的电压钳位（324）。电压钳（322）用于将锁存器（326）两端的最大电压设定为第一规定电平，并将输入级两端的最大电压设定为第二规定电平。电压转换器电路（320）在闩锁（326）和电压钳（324）之间的连接处产生第一输出信号（II）。电压转换器电路在电压钳位器（324）和输入级（322）之间的接点处产生第二输出信号（15）。

6. 发明授权

US08598941B2 Hybrid impedance compensation in a buffer circuit 有权
标题翻译：缓冲电路中的混合阻抗补偿
公开(公告)号：US08598941B2
公开(公告)日：2013-12-03
申请号：US13165195
申请日：2011-06-21
申请人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
发明人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
IPC分类号： H01L37/00
CPC分类号： H03F3/3022 , H03F1/308 , H03F1/56 , H03F2200/447
摘要： A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.
摘要翻译：用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括监视电路和与监视器电路耦合的控制电路。监视器电路包括上拉部分，其包括至少一个PMOS晶体管和包括至少一个NMOS晶体管的下拉部分。监视器电路被配置为跟踪缓冲电路的输出级的操作，并且可操作地产生至少第一控制信号，该第一控制信号指示输出中相应的上拉和下拉部分的至少一个特性的状态缓冲电路的阶段与缓冲电路可能受到的PVT条件的变化有关。控制电路用于产生作为第一控制信号的函数的一组数字控制位。该组数字控制位可用来补偿缓冲电路的输出级中的上拉和下拉部分超过规定的PVT条件变化。

7. 发明申请

US20120326768A1 Hybrid Impedance Compensation in a Buffer Circuit 有权
标题翻译：缓冲电路中的混合阻抗补偿
公开(公告)号：US20120326768A1
公开(公告)日：2012-12-27
申请号：US13165195
申请日：2011-06-21
申请人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
发明人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
IPC分类号： H03H11/40
CPC分类号： H03F3/3022 , H03F1/308 , H03F1/56 , H03F2200/447
摘要： A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.
摘要翻译：用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括监视电路和与监视器电路耦合的控制电路。监视器电路包括上拉部分，其包括至少一个PMOS晶体管和包括至少一个NMOS晶体管的下拉部分。监视器电路被配置为跟踪缓冲电路的输出级的操作，并且可操作地产生至少第一控制信号，该第一控制信号指示输出中相应的上拉和下拉部分的至少一个特性的状态缓冲电路的阶段与缓冲电路可能受到的PVT条件的变化有关。控制电路用于产生作为第一控制信号的函数的一组数字控制位。该组数字控制位可用来补偿缓冲电路的输出级中的上拉和下拉部分超过规定的PVT条件变化。

8. 发明申请

US20070229157A1 Circuit having enhanced input signal range 有权
标题翻译：电路具有增强的输入信号范围
公开(公告)号：US20070229157A1
公开(公告)日：2007-10-04
申请号：US11393171
申请日：2006-03-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F2200/513 , H03F2200/78 , H03F2203/45314 , H03F2203/45361 , H03F2203/45552 , H03F2203/45684
摘要： A circuit having an enhanced input signal range includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference between the first and second signals. The differential amplifier includes an input stage having at least first and second transistors operative to receive the first and second signals, respectively, each of the first and second transistors having a first threshold voltage associated therewith, and a load including at least third and fourth transistors having a second threshold voltage associated therewith, the first threshold voltage being greater than the second threshold voltage. The circuit further includes an output stage coupled to the differential amplifier and being operative to receive the difference signal and to generate an output signal of the circuit, the output signal being indicative of the difference signal and being referenced to the first voltage. The circuit is configured to accept the first and second signals having a voltage swing which is potentially greater than a supply voltage of the circuit.
摘要翻译：具有增强的输入信号范围的电路包括差分放大器，其可操作以接收至少第一和第二信号并放大第一和第二信号之间的差。差分放大器在其输出处产生差分信号，其作为第一和第二信号之间的差异的函数。差分放大器包括具有至少第一和第二晶体管的输入级，其中第一和第二晶体管分别用于接收第一和第二信号，第一和第二晶体管中的每一个具有与之相关联的第一阈值电压，并且负载包括至少第三和第四晶体管具有与其相关联的第二阈值电压，所述第一阈值电压大于所述第二阈值电压。电路还包括耦合到差分放大器的输出级，并且可操作以接收差分信号并产生电路的输出信号，输出信号指示差分信号并参考第一电压。电路被配置为接受具有潜在地大于电路的电源电压的电压摆幅的第一和第二信号。

9. 发明申请

US20070019348A1 Buffer circuit with enhanced overvoltage protection 有权
标题翻译：具有增强型过压保护功能的缓冲电路
公开(公告)号：US20070019348A1
公开(公告)日：2007-01-25
申请号：US11169139
申请日：2005-06-28
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
IPC分类号： H02H9/04
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A buffer circuit having enhanced overvoltage protection includes core buffer circuitry couplable to a first voltage source having a first voltage level. The core buffer circuitry is configured to receive a first signal and to generate a second signal which is a function of the first signal. The buffer circuit further includes a protection circuit coupled between the core buffer circuitry and a signal pad. The protection circuit is operative: (i) to clamp the first signal to about the first voltage level when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level.
摘要翻译：具有增强的过电压保护的缓冲电路包括可耦合到具有第一电压电平的第一电压源的核心缓冲电路。核心缓冲器电路被配置为接收第一信号并产生作为第一信号的函数的第二信号。缓冲电路还包括耦合在核心缓冲器电路和信号焊盘之间的保护电路。保护电路是可操作的：（i）当在信号焊盘处接收的第三信号超过第一电压电平达到第一量值时，将第一信号钳位到约第一电压电平; 和（ii）当第三信号小于或基本上等于第一电压电平时，产生基本上等于第三信号的第一信号。

10. 发明申请

US20060001449A1 Voltage level translator circuit 有权
公开(公告)号：US20060001449A1
公开(公告)日：2006-01-05
申请号：US10881192
申请日：2004-06-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Antonio Marques , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Antonio Marques , Bernard Morris
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for receiving the input signal. The input stage includes at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logical state of the input signal. The latch circuit includes at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp is operatively connected between the input stage and the latch circuit, the voltage clamp being configured to limit a voltage across the input stage based, at least in part, on a control signal presented thereto. The voltage level translator circuit includes a reference generator circuit for generating the control signal, a steady state value of the control signal being substantially equal to the first voltage level. The reference generator circuit is configured to adjust a voltage level of the control signal in response to the input signal.

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