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1. 发明授权

US08536925B2 Voltage level translator circuit 有权
标题翻译：电压电平转换电路
公开(公告)号：US08536925B2
公开(公告)日：2013-09-17
申请号：US12598352
申请日：2008-12-29
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Jeffrey J. Nagy , Peter J. Nicholas
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Jeffrey J. Nagy , Peter J. Nicholas
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/0375
摘要： A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).
摘要翻译：电压转换器电路（320）包括适于接收参考第一电压源（VDD核心）的输入信号的输入级（322），适于连接到第二电压源（VDD33）的锁存器（326）至少临时存储输入信号的逻辑状态，以及耦合在输入级（322）和锁存器（326）之间的电压钳位（324）。电压钳（322）用于将锁存器（326）两端的最大电压设定为第一规定电平，并将输入级两端的最大电压设定为第二规定电平。电压转换器电路（320）在闩锁（326）和电压钳（324）之间的连接处产生第一输出信号（II）。电压转换器电路在电压钳位器（324）和输入级（322）之间的接点处产生第二输出信号（15）。

2. 发明申请

US20100141334A1 Bias circuit scheme for improved reliability in high voltage supply with low voltage device 有权
标题翻译：偏压电路方案，用于提高低压电源的可靠性
公开(公告)号：US20100141334A1
公开(公告)日：2010-06-10
申请号：US12330828
申请日：2008-12-09
申请人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
发明人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
IPC分类号： G05F1/10
CPC分类号： G05F3/16
摘要： Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.
摘要翻译：公开了一种偏置电路，其中第一电阻器连接在电源电压和反馈节点之间。电阻器连接在反馈节点和参考电源电压之间。电阻之间的连接限定了至少一个偏置电压。第二电阻器连接在反馈节点和第一漏极节点之间。第一场效应晶体管具有第一栅极节点，第一漏极节点和第一源节点。门节点连接到第一电源电压。第二场效应晶体管具有第二栅极节点，第二漏极节点和第二源节点。第二排水节点连接到第一源节点。第二栅极节点连接到偏置电压。第二源节点连接到输出信号节点。输出信号节点能够经历过冲电压。

3. 发明授权

US07902904B2 Bias circuit scheme for improved reliability in high voltage supply with low voltage device 有权
标题翻译：偏压电路方案，用于提高低压电源的可靠性
公开(公告)号：US07902904B2
公开(公告)日：2011-03-08
申请号：US12330828
申请日：2008-12-09
申请人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
发明人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
IPC分类号： G05F1/10
CPC分类号： G05F3/16
摘要： Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.
摘要翻译：公开了一种偏置电路，其中第一电阻器连接在电源电压和反馈节点之间。电阻器连接在反馈节点和参考电源电压之间。电阻之间的连接限定了至少一个偏置电压。第二电阻器连接在反馈节点和第一漏极节点之间。第一场效应晶体管具有第一栅极节点，第一漏极节点和第一源节点。门节点连接到第一电源电压。第二场效应晶体管具有第二栅极节点，第二漏极节点和第二源节点。第二排水节点连接到第一源节点。第二栅极节点连接到偏置电压。第二源节点连接到输出信号节点。输出信号节点能够经历过冲电压。

4. 发明授权

US4645948A Field effect transistor current source 失效
标题翻译：场效应晶体管电流源
公开(公告)号：US4645948A
公开(公告)日：1987-02-24
申请号：US656343
申请日：1984-10-01
申请人： Bernard L. Morris , Jeffrey J. Nagy , Lawrence A. Walter
发明人： Bernard L. Morris , Jeffrey J. Nagy , Lawrence A. Walter
IPC分类号： G05F3/24 , G05F3/26 , H03K3/01 , H03K3/26 , H03K17/687
CPC分类号： G05F3/262 , Y10S323/907
摘要： A field effect transistor circuit generates a reference current that can obtain a desired temperature coefficient. The circuit is self-compensatory with respect to process variations, in that a "slow" process will produce a higher than normal current, while a "fast" process will give a lower one. This results in a tight spread of slew-rate, gain, gain-bandwidth, etc. in opamps, comparators, and other linear circuits. A simple adjustment in the circuit allows the temperature coefficient to be made positive or negative if so desired. An illustrative circuit is shown for CMOS technology, but can be applied to other field effect technologies.
摘要翻译：场效应晶体管电路产生可获得所需温度系数的参考电流。该电路对于过程变化是自补偿的，因为“慢”过程将产生高于正常电流，而“快速”过程将产生较低的电流。这导致了运算放大器，比较器和其他线性电路中压摆率，增益，增益带宽等的严格扩展。如果需要，电路中的简单调整允许温度系数为正或负。显示了CMOS技术的说明性电路，但可应用于其他场效应技术。

5. 发明授权

US4830976A Integrated circuit resistor 失效
标题翻译：集成电路电阻
公开(公告)号：US4830976A
公开(公告)日：1989-05-16
申请号：US16455
申请日：1987-02-24
申请人： Bernard L. Morris , Jeffrey J. Nagy , Lawrence A. Walter
发明人： Bernard L. Morris , Jeffrey J. Nagy , Lawrence A. Walter
IPC分类号： G05F3/26
CPC分类号： G05F3/262
摘要： An integrated circuit comprises a resistor that is formed by doping a semiconductor region that is defined by a layer, typically polysilicon, that also defines the gate electrode of field effect transistors in the integrated circuit. The well-controlled linewidth of features defined in this layer provides for tight resistor tolerance, and also allows the value of the resistor to track changes in other features defined by this layer.
摘要翻译：集成电路包括通过掺杂由通常是多晶硅限定的半导体区域形成的电阻器，其也定义了集成电路中的场效应晶体管的栅电极。该层定义的功能的良好控制线宽提供了严格的电阻容差，并且还允许电阻值跟踪此层定义的其他特征的变化。

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