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1. 发明授权

US06224690B1 Flip-Chip interconnections using lead-free solders 失效
标题翻译：使用无铅焊料的倒装芯片互连
公开(公告)号：US06224690B1
公开(公告)日：2001-05-01
申请号：US08614984
申请日：1996-03-12
申请人： Panayotis Constantinou Andricacos , Madhav Datta , Hariklia Deligianni , Wilma Jean Horkans , Sung Kwon Kang , Keith Thomas Kwietniak , Gangadhara Swami Mathad , Sampath Purushothaman , Leathen Shi , Ho-Ming Tong
发明人： Panayotis Constantinou Andricacos , Madhav Datta , Hariklia Deligianni , Wilma Jean Horkans , Sung Kwon Kang , Keith Thomas Kwietniak , Gangadhara Swami Mathad , Sampath Purushothaman , Leathen Shi , Ho-Ming Tong
IPC分类号： C22C700
CPC分类号： C22C13/02 , B23K2035/008 , B32B15/01 , C22C13/00 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/11 , H01L2224/11849 , H01L2224/119 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01061 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/30107 , H01L2224/05552 , H01L2924/00 , H01L2924/00014 , H01L2924/01074 , H01L2924/013 , H01L2924/01026
摘要： An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.
摘要翻译：适用于将微电子电路芯片连接到封装件的互连结构由本发明提供。特别地，本发明涉及通常称为C4（可控崩溃芯片连接）的区域阵列或倒装芯片技术。该结构包括沉积在钝化衬底（例如，硅晶片）上的粘附/阻挡层，任选附加的粘合层，选自Ni，Co，Fe，NiFe，NiCo，CoFe的金属的可焊层和NiCoFe，以及包含锡作为主要成分的无铅焊球和选自Bi，Ag和Sb的一种或多种合金元素，并且还可任选地包括一种或多种选自以下的元素：的Zn，In，Ni，Co和Cu。

2. 发明授权

US5937320A Barrier layers for electroplated SnPb eutectic solder joints 失效
标题翻译：电镀SnPb共晶焊点的阻隔层
公开(公告)号：US5937320A
公开(公告)日：1999-08-10
申请号：US57205
申请日：1998-04-08
申请人： Panayotis Constantinou Andricacos , Madhav Datta , Wilma Jean Horkans , Sung Kwon Kang , Keith Thomas Kwietniak
发明人： Panayotis Constantinou Andricacos , Madhav Datta , Wilma Jean Horkans , Sung Kwon Kang , Keith Thomas Kwietniak
IPC分类号： H01L23/485 , H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0347 , H01L2224/03912 , H01L2224/0401 , H01L2224/05005 , H01L2224/05027 , H01L2224/05541 , H01L2224/05572 , H01L2224/05599 , H01L2224/1147 , H01L2224/11831 , H01L2224/13006 , H01L2224/13111 , H01L2224/13116 , H01L2224/94 , H01L24/13 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/3651
摘要： The present invention provides a means of fabricating a reliable C4 flip-chip structure for low-temperature joining. The electrochemically fabricated C4 interconnection has a barrier layer between the electroplated tin-rich solder bump and the ball-limiting metallurgy that protects the terminal metal in the ball-limiting metallurgy from attack by the Sn in the solder. The barrier layer is electroplated through the same photoresist mask as the solder and thus does not require a separate patterning step. A thin layer of electroplated nickel serves as a reliable barrier layer between a copper-based ball-limiting metallurgy and a tin-lead (Sn--Pb) eutectic C4 ball.
摘要翻译：本发明提供了制造用于低温接合的可靠的C4倒装芯片结构的方法。电化学制造的C4互连在电镀的富含锡的焊料凸块和限制极限冶金之间具有阻挡层，其保护极限冶金学中的端子金属不被焊料中的Sn的侵蚀。阻挡层通过与焊料相同的光致抗蚀剂掩模电镀，因此不需要单独的图案化步骤。电镀镍薄层在铜基极限冶金和锡铅（Sn-Pb）共晶C4球之间作为可靠的阻挡层。

3. 发明授权

US06709562B1 Method of making electroplated interconnection structures on integrated circuit chips 有权
标题翻译：在集成电路芯片上制作电镀互连结构的方法
公开(公告)号：US06709562B1
公开(公告)日：2004-03-23
申请号：US09348632
申请日：1999-07-06
申请人： Panayotis Constantinou Andricacos , Hariklia Deligianni , John Owen Dukovic , Daniel Charles Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth Parker Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
发明人： Panayotis Constantinou Andricacos , Hariklia Deligianni , John Owen Dukovic , Daniel Charles Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth Parker Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
IPC分类号： C25D712
CPC分类号： H01L21/2885 , C25D3/38 , C25D7/123 , H01L21/76877
摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
摘要翻译：描述了用于制造用于集成电路芯片的亚微米互连结构的过程。通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。这种方法在不留下空隙或接缝的情况下超滤特征的能力是独一无二的，优于其他沉积方法。以这种方式使用电镀Cu的结构的电迁移电阻优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

4. 发明授权

US06406608B1 Apparatus to monitor and add plating solution to plating baths and controlling quality of deposited metal 失效
标题翻译：用于监测和添加电镀溶液到电镀槽并控制沉积金属质量的设备
公开(公告)号：US06406608B1
公开(公告)日：2002-06-18
申请号：US09631679
申请日：2000-08-02
申请人： Cyprian Emeka Uzoh , Wilma Jean Horkans , Panayotis Constantinou Andricacos
发明人： Cyprian Emeka Uzoh , Wilma Jean Horkans , Panayotis Constantinou Andricacos
IPC分类号： C25D2118
CPC分类号： C25D21/14 , C25D21/18
摘要： An apparatus for monitoring and adding solution to a plating bath and controlling the quality of deposited metal. At least one monitor monitors at least one condition within a plating bath and produces at least one signal corresponding to the at least one condition. At least one controller receives the at least one signal produced by the at least one monitor, processes the at least one signal, determines whether an additional amount of at least one chemical should be added to the plating bath, and controls at least one valve for controlling flow of the additional amount of the at least one chemical. A pre-mix tank pre-mixes chemicals to be added to the tank. A plurality of holding tanks holds chemicals and supplies the chemicals to the pre-mix tank. At least one valve is arranged between each holding tank and the pre-mix tank. At least one valve is also arranged between the pre-mix tank and the plating bath.
摘要翻译：一种用于监测和添加镀液溶液并控制沉积金属质量的装置。至少一个监视器监测电镀槽内的至少一个状况，并产生至少一个对应于至少一个条件的信号。至少一个控制器接收由至少一个监视器产生的至少一个信号，处理该至少一个信号，确定是否应当向镀浴添加额外量的至少一种化学品，并且控制至少一个阀用于控制附加量的至少一种化学品的流动。预混罐预混合添加到罐中的化学物质。多个容纳罐容纳化学品并将化学品供应到预混合罐中。每个保持槽和预混罐之间至少安装一个阀。在预混合槽和电镀槽之间还设置至少一个阀。

5. 发明授权

US6113769A Apparatus to monitor and add plating solution of plating baths and controlling quality of deposited metal 失效
标题翻译：用于监测和添加电镀液的镀液和控制沉积金属质量的装置
公开(公告)号：US6113769A
公开(公告)日：2000-09-05
申请号：US975756
申请日：1997-11-21
申请人： Cyprian Emeka Uzoh , Wilma Jean Horkans , Panayotis Constantinou Andricacos
发明人： Cyprian Emeka Uzoh , Wilma Jean Horkans , Panayotis Constantinou Andricacos
IPC分类号： C25D21/14 , C25D21/18 , C25B15/00
CPC分类号： C25D21/14 , C25D21/18
摘要： An apparatus for monitoring and adding solution to a plating bath and controlling the quality of deposited metal. At least one monitor monitors at least one condition within a plating bath and produces at least one signal corresponding to the at least one condition. At least one controller receives the at least one signal produced by the at least one monitor, processes the at least one signal, determines whether an additional amount of at least one chemical should be added to the plating bath, and controls at least one valve for controlling flow of the additional amount of the at least one chemical. A pre-mix tank pre-mixes chemicals to be added to the tank. A plurality of holding tanks holds chemicals and supplies the chemicals to the pre-mix tank. At least one valve is arranged between each holding tank and the pre-mix tank. At least one valve is also arranged between the pre-mix tank and the plating bath.
摘要翻译：一种用于监测和添加镀液溶液并控制沉积金属质量的装置。至少一个监视器监测电镀槽内的至少一个状况，并产生至少一个对应于至少一个条件的信号。至少一个控制器接收由至少一个监视器产生的至少一个信号，处理该至少一个信号，确定是否应当向镀浴添加额外量的至少一种化学品，并且控制至少一个阀用于控制附加量的至少一种化学品的流动。预混罐预混合添加到罐中的化学物质。多个容纳罐容纳化学品并将化学品供应到预混合罐中。每个保持槽和预混罐之间至少安装一个阀。在预混合槽和电镀槽之间还设置至少一个阀。

6. 发明授权

US06946716B2 Electroplated interconnection structures on integrated circuit chips 有权
标题翻译：集成电路芯片上的电镀互连结构
公开(公告)号：US06946716B2
公开(公告)日：2005-09-20
申请号：US10773434
申请日：2004-02-09
申请人： Panayotis Constantinou Andricacos , Harikilia Deligianni , John Owen Dukovic , Daniel C. Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth P. Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
发明人： Panayotis Constantinou Andricacos , Harikilia Deligianni , John Owen Dukovic , Daniel C. Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth P. Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
IPC分类号： H01L21/288 , H01L21/768 , H01L29/00
CPC分类号： C25D3/38 , C25D5/022 , H01L21/2885 , H01L21/76877 , H01L21/76885
摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
摘要翻译：描述了用于制造用于集成电路芯片的亚微米互连结构的过程。通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。这种方法在不留下空隙或接缝的情况下超量填充特征的能力是独一无二的，优于其他沉积方法。以这种方式电镀Cu的结构的电迁移阻力优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

7. 发明授权

US06570255B2 Method for forming interconnects on semiconductor substrates and structures formed 失效
公开(公告)号：US06570255B2
公开(公告)日：2003-05-27
申请号：US10191015
申请日：2002-07-08
申请人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , John Michael Cotte , Lynne Gignac , Wilma Jean Horkans , Kenneth Parker Rodbell
发明人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , John Michael Cotte , Lynne Gignac , Wilma Jean Horkans , Kenneth Parker Rodbell
IPC分类号： H01L2348
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.

8. 发明授权

US06429523B1 Method for forming interconnects on semiconductor substrates and structures formed 失效
标题翻译：在半导体衬底上形成互连的方法和形成的结构
公开(公告)号：US06429523B1
公开(公告)日：2002-08-06
申请号：US09755899
申请日：2001-01-04
申请人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , John Michael Cotte , Lynne Gignac , Wilma Jean Horkans , Kenneth Parker Rodbell
发明人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , John Michael Cotte , Lynne Gignac , Wilma Jean Horkans , Kenneth Parker Rodbell
IPC分类号： H01L2348
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.
摘要翻译：公开了一种在半导体结构中形成金属互连的方法和形成的结构。在该方法中，首先将第一金属的晶种层沉积到互连开口中，其中晶种层的平均晶粒尺寸至少为0.0005μm。然后将半导体结构在足以将种子层中的平均晶粒尺寸生长至至少膜厚度的温度下退火。然后沉积第二金属的填料层以填充覆盖种子层的互连开口，使得填充层的平均粒度大于0.0005μm，并且与退火种子层相当。

9. 发明授权

US06974531B2 Method for electroplating on resistive substrates 失效
公开(公告)号：US06974531B2
公开(公告)日：2005-12-13
申请号：US10269956
申请日：2002-10-15
申请人： Panayotis Andricacos , Hariklia Deligianni , Wilma Jean Horkans , Keith T. Kwietniak , Michael Lane , Sandra G. Malhotra , Fenton Read McFeely , Conal Murray , Kenneth P. Rodbell , Philippe M. Vereecken
发明人： Panayotis Andricacos , Hariklia Deligianni , Wilma Jean Horkans , Keith T. Kwietniak , Michael Lane , Sandra G. Malhotra , Fenton Read McFeely , Conal Murray , Kenneth P. Rodbell , Philippe M. Vereecken
IPC分类号： C25D5/18 , C25D7/12 , B32B15/00
CPC分类号： C25D5/18 , C25D7/12 , Y10S428/926 , Y10T428/12493 , Y10T428/12528 , Y10T428/12771 , Y10T428/12778 , Y10T428/12903
摘要： A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

10. 发明授权

US06592747B2 Method of controlling additives in copper plating baths 有权
标题翻译：控制镀铜浴中添加剂的方法
公开(公告)号：US06592747B2
公开(公告)日：2003-07-15
申请号：US09881817
申请日：2001-06-18
申请人： Wilma Jean Horkans , Keith T. Kwietniak , Peter S. Locke
发明人： Wilma Jean Horkans , Keith T. Kwietniak , Peter S. Locke
IPC分类号： G01N2742
CPC分类号： G01N31/164 , G01N27/42
摘要： Organic addition agents in copper plating baths are monitored by diluting a sample of the bath with sulfuric acid and hydrochloric acid and optionally a cupric salt. The diluting provides a bath having conventional concentrations of cupric ion, sulfuric acid and hydrochloric acid; and adjusted concentrations of the organic addition agents of 1/X of their original values in the sample; where X is the dilution factor. CVS techniques are used to determine concentrations of organic addition agents.
摘要翻译：通过用硫酸和盐酸和任选的铜盐稀释浴的样品来监测铜电镀浴中的有机添加剂。稀释液提供具有常规浓度的铜离子，硫酸和盐酸的浴液; 并将样品中原始值的1 / X的有机添加剂的浓度调节到其中; 其中X是稀释因子。 CVS技术用于确定有机添加剂的浓度。

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