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1. 发明授权

US07212091B2 Micro-electro-mechanical RF switch 有权
标题翻译：微机电RF开关
公开(公告)号：US07212091B2
公开(公告)日：2007-05-01
申请号：US11053732
申请日：2005-02-08
申请人： Panayotis Constantinou Andricacos , L. Paivikki Buchwalter , Hariklia Deligianni , Robert A. Groves , Christopher Jahnes , Jennifer L. Lund , Michael Meixner , David Earle Seeger , Timothy D. Sullivan , Ping-Chuan Wang
发明人： Panayotis Constantinou Andricacos , L. Paivikki Buchwalter , Hariklia Deligianni , Robert A. Groves , Christopher Jahnes , Jennifer L. Lund , Michael Meixner , David Earle Seeger , Timothy D. Sullivan , Ping-Chuan Wang
IPC分类号： H01H51/22
CPC分类号： H01H59/0009 , H01H2001/0078
摘要： A microelectromechanical switch including: at least one pair of actuator electrodes; at least one input electrode and at least one output electrode for input and output, respectively, of a radio frequency signal; and a beam movable by an attraction between the at least one pair of actuator electrodes, the movable beam having at least a portion electrically connected to the at least one input electrode and to the at least one output electrode when moved by the attraction between the at least one pair of actuator electrodes to make an electrical connection between the at least one input and output electrodes; wherein the at least one pair of actuator electrodes are electrically isolated from each of the at least one input and output electrodes. The microelectromechanical switch can be configured in single or multiple-poles and/or single or multiple throws.
摘要翻译：一种微机电开关，包括：至少一对致动器电极; 分别输入和输出射频信号的至少一个输入电极和至少一个输出电极; 以及可由所述至少一对致动器电极之间的吸引部移动的光束，所述可移动光束具有至少一部分电连接到所述至少一个输入电极，并且当所述至少一个输入电极在所述至少一个输入电极之间被所述吸引力移动时，至少一对致动器电极，用于在所述至少一个输入和输出电极之间形成电连接; 其中所述至少一对致动器电极与所述至少一个输入和输出电极中的每一个电隔离。微机电开关可以配置为单极或多极和/或单掷或多掷。

2. 发明授权

US06876282B2 Micro-electro-mechanical RF switch 失效
标题翻译：微机电RF开关
公开(公告)号：US06876282B2
公开(公告)日：2005-04-05
申请号：US10150285
申请日：2002-05-17
申请人： Panayotis Constantinou Andricacos , L. Paivikki Buchwalter , Hariklia Deligianni , Robert A. Groves , Christopher Jahnes , Jennifer L. Lund , Michael Meixner , David Earle Seeger , Timothy D. Sullivan , Ping-Chuan Wang
发明人： Panayotis Constantinou Andricacos , L. Paivikki Buchwalter , Hariklia Deligianni , Robert A. Groves , Christopher Jahnes , Jennifer L. Lund , Michael Meixner , David Earle Seeger , Timothy D. Sullivan , Ping-Chuan Wang
IPC分类号： H01H59/00 , H01H51/22
CPC分类号： H01H59/0009 , H01H2001/0078
摘要： A microelectromechanical switch including: at least one pair of actuator electrodes; at least one input electrode and at least one output electrode for input and output, respectively, of a radio frequency signal; and a beam movable by an attraction between the at least one pair of actuator electrodes, the movable beam having at least a portion electrically connected to the at least one input electrode and to the at least one output electrode when moved by the attraction between the at least one pair of actuator electrodes to make an electrical connection between the at least one input and output electrodes; wherein the at least one pair of actuator electrodes are electrically isolated from each of the at least one input and output electrodes. The microelectromechanical switch can be configured in single or multiple-poles and/or single or multiple throws.
摘要翻译：一种微机电开关，包括：至少一对致动器电极; 分别输入和输出射频信号的至少一个输入电极和至少一个输出电极; 以及可由所述至少一对致动器电极之间的吸引部移动的光束，所述可移动光束具有至少一部分电连接到所述至少一个输入电极，并且当所述至少一个输入电极在所述至少一个输入电极之间被所述吸引力移动时，至少一对致动器电极，用于在所述至少一个输入和输出电极之间形成电连接; 其中所述至少一对致动器电极与所述至少一个输入和输出电极中的每一个电隔离。微机电开关可以配置为单极或多极和/或单掷或多掷。

3. 发明授权

US06709562B1 Method of making electroplated interconnection structures on integrated circuit chips 有权
标题翻译：在集成电路芯片上制作电镀互连结构的方法
公开(公告)号：US06709562B1
公开(公告)日：2004-03-23
申请号：US09348632
申请日：1999-07-06
申请人： Panayotis Constantinou Andricacos , Hariklia Deligianni , John Owen Dukovic , Daniel Charles Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth Parker Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
发明人： Panayotis Constantinou Andricacos , Hariklia Deligianni , John Owen Dukovic , Daniel Charles Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth Parker Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
IPC分类号： C25D712
CPC分类号： H01L21/2885 , C25D3/38 , C25D7/123 , H01L21/76877
摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
摘要翻译：描述了用于制造用于集成电路芯片的亚微米互连结构的过程。通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。这种方法在不留下空隙或接缝的情况下超滤特征的能力是独一无二的，优于其他沉积方法。以这种方式使用电镀Cu的结构的电迁移电阻优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

4. 发明授权

US06224690B1 Flip-Chip interconnections using lead-free solders 失效
标题翻译：使用无铅焊料的倒装芯片互连
公开(公告)号：US06224690B1
公开(公告)日：2001-05-01
申请号：US08614984
申请日：1996-03-12
申请人： Panayotis Constantinou Andricacos , Madhav Datta , Hariklia Deligianni , Wilma Jean Horkans , Sung Kwon Kang , Keith Thomas Kwietniak , Gangadhara Swami Mathad , Sampath Purushothaman , Leathen Shi , Ho-Ming Tong
发明人： Panayotis Constantinou Andricacos , Madhav Datta , Hariklia Deligianni , Wilma Jean Horkans , Sung Kwon Kang , Keith Thomas Kwietniak , Gangadhara Swami Mathad , Sampath Purushothaman , Leathen Shi , Ho-Ming Tong
IPC分类号： C22C700
CPC分类号： C22C13/02 , B23K2035/008 , B32B15/01 , C22C13/00 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/11 , H01L2224/11849 , H01L2224/119 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01061 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/30107 , H01L2224/05552 , H01L2924/00 , H01L2924/00014 , H01L2924/01074 , H01L2924/013 , H01L2924/01026
摘要： An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.
摘要翻译：适用于将微电子电路芯片连接到封装件的互连结构由本发明提供。特别地，本发明涉及通常称为C4（可控崩溃芯片连接）的区域阵列或倒装芯片技术。该结构包括沉积在钝化衬底（例如，硅晶片）上的粘附/阻挡层，任选附加的粘合层，选自Ni，Co，Fe，NiFe，NiCo，CoFe的金属的可焊层和NiCoFe，以及包含锡作为主要成分的无铅焊球和选自Bi，Ag和Sb的一种或多种合金元素，并且还可任选地包括一种或多种选自以下的元素：的Zn，In，Ni，Co和Cu。

5. 发明授权

US06090710A Method of making copper alloys for chip and package interconnections 失效
标题翻译：制造用于芯片和封装互连的铜合金的方法
公开(公告)号：US06090710A
公开(公告)日：2000-07-18
申请号：US911808
申请日：1997-08-15
申请人： Panayotis Constantinou Andricacos , Hariklia Deligianni , James McKell Edwin Harper , Chao-Kun Hu , Dale Jonathan Pearson , Scott Kevin Reynolds , King-Ning Tu , Cyprian Emeka Uzoh
发明人： Panayotis Constantinou Andricacos , Hariklia Deligianni , James McKell Edwin Harper , Chao-Kun Hu , Dale Jonathan Pearson , Scott Kevin Reynolds , King-Ning Tu , Cyprian Emeka Uzoh
IPC分类号： C22C9/00 , C22C9/02 , H01L21/768 , H01L23/48 , H01L23/498 , H01L23/532 , H01L21/44
CPC分类号： H01L23/49866 , H01L21/76834 , H01L21/76883 , H01L21/76885 , H01L23/49822 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10T428/12014 , Y10T428/12903 , Y10T428/265
摘要： A method of making Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin is disclosed for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.
摘要翻译：公开了一种制备含有0.01至10重量％的至少一种选自碳，铟和锡的合金元素的铜合金的方法，用于改善可用于芯片和封装互连和导体的电迁移率，低电阻率和良好的耐腐蚀性通过首先形成铜合金，然后退火以使合金元素向合金中的晶粒之间的晶界扩散。

6. 发明授权

US6063506A Copper alloys for chip and package interconnections 失效
标题翻译：用于芯片和封装互连的铜合金
公开(公告)号：US6063506A
公开(公告)日：2000-05-16
申请号：US093500
申请日：1998-06-08
申请人： Panayotis Constantinou Andricacos , Hariklia Deligianni , James McKell Edwin Harper , Chao-Kun Hu , Dale Jonathan Pearson , Scott Kevin Reynolds , King-Ning Tu , Cyprian Emeka Uzoh
发明人： Panayotis Constantinou Andricacos , Hariklia Deligianni , James McKell Edwin Harper , Chao-Kun Hu , Dale Jonathan Pearson , Scott Kevin Reynolds , King-Ning Tu , Cyprian Emeka Uzoh
IPC分类号： C22C9/00 , C22C9/02 , H01L21/768 , H01L23/48 , H01L23/498 , H01L23/532 , B32B15/20 , H01B5/02 , H01L21/44
CPC分类号： H01L23/49866 , H01L21/76834 , H01L21/76883 , H01L21/76885 , H01L23/49822 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10T428/12014 , Y10T428/12903 , Y10T428/265
摘要： Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and a method of making such interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.
摘要翻译：含有0.01至10重量％的至少一种选自碳，铟和锡的合金元素的铜合金，用于改善电迁移率，低电阻率和良好的耐腐蚀性，可用于芯片和封装互连，以及制造这种互连和导体，首先形成铜合金，然后退火以使合金元素向合金中的晶粒之间的晶界扩散。

7. 发明授权

US5789320A Plating of noble metal electrodes for DRAM and FRAM 失效
标题翻译：电镀DRAM和FRAM的贵金属电极
公开(公告)号：US5789320A
公开(公告)日：1998-08-04
申请号：US636456
申请日：1996-04-23
申请人： Panayotis Constantinou Andricacos , James Hartfiel Comfort , Alfred Grill , David Edward Kotecki , Vishnubhai Vitthalbhai Patel , Katherine Lynn Saenger , Alejandro Gabriel Schrott
发明人： Panayotis Constantinou Andricacos , James Hartfiel Comfort , Alfred Grill , David Edward Kotecki , Vishnubhai Vitthalbhai Patel , Katherine Lynn Saenger , Alejandro Gabriel Schrott
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/44
CPC分类号： H01L27/1085 , H01L28/60
摘要： Noble metal plating on a preexisting seed layer is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective case, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.
摘要翻译：用于DRAM和FRAM的电极的制造中使用预先存在的种子层上的贵金属电镀。电镀可以是空间选择性的或非选择性的。在非选择性情况下，首先将覆盖膜镀覆，然后通过空间选择性材料去除在沉积后进行图案化。在选择性情况下，电镀沉积物可以通过通孔掩模技术在光刻定义的区域中选择性地生长，或者在预先存在的电极结构的暴露区域上选择性地生长为保形涂层。在电镀工艺中可以使用类金刚石碳膜。公开了一种自对准工艺，用于在通过掩模工艺中选择性地涂覆绝缘体。

8. 发明授权

US5825609A Compound electrode stack capacitor 失效
标题翻译：复合电极堆叠电容器
公开(公告)号：US5825609A
公开(公告)日：1998-10-20
申请号：US636457
申请日：1996-04-23
申请人： Panayotis Constantinou Andricacos , David Edward Kotecki , Katherine Lynn Saenger
发明人： Panayotis Constantinou Andricacos , David Edward Kotecki , Katherine Lynn Saenger
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , H01G4/06
CPC分类号： H01L28/82 , H01L21/76849 , H01L21/7687 , H01L27/1085 , H01L28/91 , H01L28/55
摘要： This invention is directed to a semiconductor memory device including a storage element having a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.
摘要翻译：本发明涉及一种半导体存储器件，其包括在顶部（板）电极和底部（堆叠）电极之间具有铁电材料或电容器电介质材料的存储元件。特别地，本发明涉及堆叠电极的设计和制造，其被描述为化合物，因为它由两种或更多种材料组成，这两种或多种材料是单独图案化的（至少一种材料在沉积之前沉积和图案化其他），或者被布置成使得每个组分材料显着地有助于初始沉积铁电体或电容器电介质的区域。相对于相同尺寸的固体单材料电极，这些复合堆叠电极可以提供易于处理，更经济地使用贵金属材料以及潜在的增加的机械稳定性（例如抵抗小丘）。

9. 发明授权

US06268291B1 Method for forming electromigration-resistant structures by doping 有权
标题翻译：通过掺杂形成电迁移结构的方法
公开(公告)号：US06268291B1
公开(公告)日：2001-07-31
申请号：US09204185
申请日：1998-12-03
申请人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Christopher Carr Parks , Kenneth Parker Rodbell , Roger Yen-Luen Tsai
发明人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Christopher Carr Parks , Kenneth Parker Rodbell , Roger Yen-Luen Tsai
IPC分类号： H01L2100
CPC分类号： H01L21/2885 , H01L21/76843 , H01L21/76855 , H01L21/76858 , H01L21/76859 , H01L21/76864 , H01L21/76873 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L23/53233 , H01L23/53238 , H01L2924/00013 , H01L2924/0002 , H01L2224/29099 , H01L2924/00
摘要： A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved is disclosed. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by three different methods. In the first method, a copper seed layer is first deposited into a receptacle and an ion implantation process is carried out on the seed layer, which is followed by electroplating copper into the receptacle. In the second method, a copper seed layer is first deposited into a receptacle, a copper composition containing impurities is then electrodeposited into the receptacle and the electronic structure is annealed so that impurities diffuse into the copper seed layer. In the third method, a barrier layer is first deposited into a receptacle, dopant ions are then implanted into the barrier layer with a copper seed layer subsequently deposited on top of the barrier layer. An annealing process for the electronic structure is then carried out such that dopant ions diffuse into the copper seed layer. The present invention method may further include the step of ion-implanting at least one element into a surface layer of the copper conductor after the conductor is first planarized. The surface layer may have a thickness between about 30 Å and about 500 Å. At least one element may be selected from Co, Al, Sn, In, Ti and Cr.
摘要翻译：本发明公开了一种在电子结构中形成铜导体的方法，该方法是先将铜组合物沉积在形成于电子结构中的容器中，然后向铜组合物中添加杂质使其电迁移阻力得到改善。在该方法中，铜组合物可以通过各种技术沉积，例如电镀，物理气相沉积和化学气相沉积。可植入的杂质包括C，O，Cl，S和N的杂质，其浓度范围为约0.01ppm至约1000ppm。可以通过三种不同的方法加入杂质。在第一种方法中，首先将铜种子层沉积到容器中，并在种子层上进行离子注入工艺，然后将铜电镀到容器中。在第二种方法中，首先将铜种子层沉积到容器中，然后将含有杂质的铜组合物电沉积到容器中，并且将电子结构退火，使得杂质扩散到铜籽晶层中。在第三种方法中，首先将阻挡层沉积到容器中，然后将掺杂剂离子注入到阻挡层中，随后将铜籽晶层沉积在阻挡层的顶部上。然后进行电子结构的退火处理，使得掺杂剂离子扩散到铜籽晶层中。本发明的方法还可以包括在导体首先平坦化之后将至少一种元素离子注入到铜导体的表面层中的步骤。表面层可以具有在约和之间的厚度。至少一种元素可以选自Co，Al，Sn，In，Ti和Cr。

10. 发明授权

US06406608B1 Apparatus to monitor and add plating solution to plating baths and controlling quality of deposited metal 失效
标题翻译：用于监测和添加电镀溶液到电镀槽并控制沉积金属质量的设备
公开(公告)号：US06406608B1
公开(公告)日：2002-06-18
申请号：US09631679
申请日：2000-08-02
申请人： Cyprian Emeka Uzoh , Wilma Jean Horkans , Panayotis Constantinou Andricacos
发明人： Cyprian Emeka Uzoh , Wilma Jean Horkans , Panayotis Constantinou Andricacos
IPC分类号： C25D2118
CPC分类号： C25D21/14 , C25D21/18
摘要： An apparatus for monitoring and adding solution to a plating bath and controlling the quality of deposited metal. At least one monitor monitors at least one condition within a plating bath and produces at least one signal corresponding to the at least one condition. At least one controller receives the at least one signal produced by the at least one monitor, processes the at least one signal, determines whether an additional amount of at least one chemical should be added to the plating bath, and controls at least one valve for controlling flow of the additional amount of the at least one chemical. A pre-mix tank pre-mixes chemicals to be added to the tank. A plurality of holding tanks holds chemicals and supplies the chemicals to the pre-mix tank. At least one valve is arranged between each holding tank and the pre-mix tank. At least one valve is also arranged between the pre-mix tank and the plating bath.
摘要翻译：一种用于监测和添加镀液溶液并控制沉积金属质量的装置。至少一个监视器监测电镀槽内的至少一个状况，并产生至少一个对应于至少一个条件的信号。至少一个控制器接收由至少一个监视器产生的至少一个信号，处理该至少一个信号，确定是否应当向镀浴添加额外量的至少一种化学品，并且控制至少一个阀用于控制附加量的至少一种化学品的流动。预混罐预混合添加到罐中的化学物质。多个容纳罐容纳化学品并将化学品供应到预混合罐中。每个保持槽和预混罐之间至少安装一个阀。在预混合槽和电镀槽之间还设置至少一个阀。

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