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1. 发明授权

US5159688A Information processor performing interrupt operation in two modes 失效
标题翻译：信息处理器在两种模式下执行中断操作
公开(公告)号：US5159688A
公开(公告)日：1992-10-27
申请号：US691284
申请日：1991-04-25
申请人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
发明人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
IPC分类号： G06F13/32
CPC分类号： G06F13/32
摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

2. 发明授权

US5163150A Information processor performing interrupt operation without saving contents of program counter 失效
标题翻译：信息处理器执行中断操作，而不保存程序计数器的内容
公开(公告)号：US5163150A
公开(公告)日：1992-11-10
申请号：US691297
申请日：1991-04-25
申请人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
发明人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
IPC分类号： G06F13/32
CPC分类号： G06F13/32
摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs and interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.
摘要翻译：信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。当处理器根据来自外围设备的请求执行和中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新启动由中断到堆栈存储器的程序执行所必需的信息的堆栈操作。虽然处理器可以在没有堆栈操作的情况下响应于第二模式信号执行中断操作，从而可以提供具有较少开销的改进的处理器。

3. 发明授权

US5036458A Information processor executing interruption program without saving contents of program counter 失效
标题翻译：信息处理器执行中断程序，而不保存程序计数器的内容
公开(公告)号：US5036458A
公开(公告)日：1991-07-30
申请号：US287622
申请日：1988-12-20
申请人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
发明人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
IPC分类号： G06F13/32
CPC分类号： G06F13/32
摘要： An information processor has at least one interface unit by which the processor is coupled to peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart execution of a program which is stopped by the interruption in a stack memory is performed before the start of the interruption operation. The processor can perform the interruption operation in response to the second mode signal without the stack operation, providing an improved processor with less overhead. The two interruption mode technique is described in a number of applications, including D/A conversion, serial data transmission and reception, and operation of computer peripheral devices.
摘要翻译：信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。当处理器根据来自外围设备的请求执行中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新执行由堆栈存储器中的中断而停止的程序所需的信息的堆栈操作。处理器可以在不进行堆栈操作的情况下响应于第二模式信号执行中断操作，从而提供具有较少开销的改进的处理器。在多种应用中描述了两种中断模式技术，包括D / A转换，串行数据传输和接收以及计算机外围设备的操作。

4. 发明授权

US4984190A Serial data transfer system 失效
标题翻译：串行数据传输系统
公开(公告)号：US4984190A
公开(公告)日：1991-01-08
申请号：US569539
申请日：1990-08-20
申请人： Shigetatsu Katori , Yukio Maehashi , Yukari Misawa
发明人： Shigetatsu Katori , Yukio Maehashi , Yukari Misawa
IPC分类号： G06F13/28 , G06F13/42 , G06F15/17
CPC分类号： G06F13/423 , G06F13/28 , G06F15/17
摘要： Herein disclosed is a serial data transfer system which has first and second serial data processors connected via a single data line and a single clock line for transferring serial data therebetween. Each of the first and second serial data processors includes: reception confirmation signal output means for outputting a reception confirmation signal to the data line; and reception confirmation signal detection means for detecting the reception confirmation signal on the data line. The confirmation of the data transfer is executed in synchronism with serial clock pulses outputted to the clock line. Alternatively, the first or second serial data processor includes: an output circuit for outputting a reception confirmation signal to the data line; a circuit for generating a first signal indicating the end of reception of the serial data; a circuit for generating a second signal indicating the end of processing of the data received; and a circuit for controlling the output of said reception confirmation signal. When the reception of the serial data on the data line is ended, the output circuit outputs the reception confirmation signal to the data line in synchronism with the first or second signal.
摘要翻译：这里公开了一种串行数据传输系统，其具有通过单个数据线连接的第一和第二串行数据处理器以及用于在其间传送串行数据的单个时钟线。第一和第二串行数据处理器中的每一个包括：接收确认信号输出装置，用于向数据线输出接收确认信号; 以及接收确认信号检测装置，用于检测数据线上的接收确认信号。与输出到时钟线的串行时钟脉冲同步执行数据传送的确认。或者，第一或第二串行数据处理器包括：输出电路，用于向数据线输出接收确认信号; 用于产生指示串行数据的接收结束的第一信号的电路; 用于产生指示所接收的数据的处理结束的第二信号的电路; 以及用于控制所述接收确认信号的输出的电路。当数据线上的串行数据的接收结束时，输出电路与第一或第二信号同步地向数据线输出接收确认信号。

5. 发明授权

US4847867A Serial bus interface system for data communication using two-wire line as clock bus and data bus 失效
标题翻译：串行总线接口系统，用于使用双线线路作为时钟总线和数据总线的数据通信
公开(公告)号：US4847867A
公开(公告)日：1989-07-11
申请号：US91803
申请日：1987-09-01
申请人： Masaki Nasu , Shigetatsu Katori , Yukio Maehashi , Kazutoshi Yoshizawa
发明人： Masaki Nasu , Shigetatsu Katori , Yukio Maehashi , Kazutoshi Yoshizawa
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4077 , G06F13/4256
摘要： A serial data communication system is disclosed. This system includes a plurality of stations which are interconnected by a single clock wire and a single data wire. A master station in the stations includes a transistor push-pull circuit for driving the clock wire to output a clock signal on the clock wire. The clock signal thus has sharp leading and falling edges. The data wire is coupled to wire logic means. A transmitting station transmits each bit of a data signal on the data wire in synchronism with one of leading and falling edges of the associated clock pulse of the clock signal, and a receiving station receives each bit of the data signal in synchronism with the other of leading and falling edges of the associated clock pulse.
摘要翻译：公开了一种串行数据通信系统。该系统包括通过单个时钟线和单个数据线互连的多个站。站中的主站包括用于驱动时钟线的晶体管推挽电路，以在时钟线上输出时钟信号。因此，时钟信号具有尖锐的引导和下降沿。数据线耦合到线逻辑装置。发送站与时钟信号的相关联的时钟脉冲的前沿和下降沿中的一个同步地在数据线上传输数据信号的每一位，并且接收站与另一个的同步接收数据信号的每一位相关时钟脉冲的前沿和下降沿。

6. 发明授权

US4839797A Microprocessor compatible with any software represented by different types of instruction formats 失效
标题翻译：微处理器与由不同类型的指令格式表示的任何软件兼容
公开(公告)号：US4839797A
公开(公告)日：1989-06-13
申请号：US759006
申请日：1985-07-25
申请人： Shigetatsu Katori , Yukio Maehashi
发明人： Shigetatsu Katori , Yukio Maehashi
IPC分类号： G06F9/30 , G06F9/318 , G06F9/455
CPC分类号： G06F9/30174 , G06F9/30189
摘要： A microprocessor includes a central processing unit which executes a program according to at least one control signal generated by an instruction decoder. The instruction decoder is designed such that a first type instruction compatible for the central processing unit can be decoded. A second type instruction not compatible for the central processing unit is applied as an address to a conversion memory in which a first type instruction corresponding in function to the second type instruction has been stored. The first type instruction in the conversion memory is then applied to the instruction decoder instead of the second type instruction. Thus, the second type instruction can be executed by the central processing unit which is not otherwise compatible with the second type instruction.
摘要翻译：微处理器包括中央处理单元，该中央处理单元根据由指令解码器产生的至少一个控制信号来执行程序。指令解码器被设计成使得能够解码与中央处理单元兼容的第一类型指令。将不兼容中央处理单元的第二类型指令作为地址应用于其中已经存储了与第二类型指令功能相对应的第一类型指令的转换存储器。然后转换存储器中的第一类型指令被施加到指令解码器而不是第二类型指令。因此，第二类型的指令可以由与第二类型指令不兼容的中央处理单元执行。

7. 发明授权

US4964141A Serial data processor capable of transferring data at a high speed 失效
标题翻译：能够高速传输数据的串行数据处理器
公开(公告)号：US4964141A
公开(公告)日：1990-10-16
申请号：US182006
申请日：1988-04-15
申请人： Osamu Matsushima , Yukio Maehashi
发明人： Osamu Matsushima , Yukio Maehashi
IPC分类号： G06F13/38 , G06F13/00 , H04L1/16 , H04L5/16 , H04L7/00 , H04L7/04 , H04L29/08
CPC分类号： H04L7/0008 , H04L5/16 , H04L1/1692
摘要： A serial data processor is coupled to a single data line and a single clock line for serial data transfer in synchronism with a clock signal. The data processor comprises a shift register coupled to the serial data line and operated to serially output the data in synchronism with a clock on the clock line, and an output buffer connected to receive the data serially outputted from the shift register and coupled to sequentially output the received data to the data line. This output buffer includes a push-pull driver having an output connected to the data line and an input driven by the data serially outputted from the shift register. A clock counter is coupled to receive the clock on the clock line so as to maintain the push-pull driver in an operable condition until the count value reaches a predetermined value and to bring the output of the push-pull driver into a floating condition after the count value reached a predetermined value. There is provided a data line control circuit coupled to the data line and controlled by the clock counter to bring the data line to a high level after the count value of the clock counter reaches the predetermined value.

8. 发明授权

US4953082A Master processor providing tokens to dataflow processor for controlling instructions execution and data store operation 失效
标题翻译：主处理器为数据流处理器提供令牌，用于控制指令执行和数据存储操作
公开(公告)号：US4953082A
公开(公告)日：1990-08-28
申请号：US310577
申请日：1989-02-15
申请人： Masahiro Nomura , Yukio Maehashi
发明人： Masahiro Nomura , Yukio Maehashi
IPC分类号： G06F15/167 , G06F9/38 , G06F9/44 , G06F15/82
CPC分类号： G06F9/3889 , G06F9/3879 , G06F9/4436
摘要： An information processing apparatus with a dual processor system contains a general purpose processor for processing a required program and a special purpose processor for processing a specific operation in the required program. The special purpose processor is designed according to a data flow architecture and executes a task according to a token prepared by the general purpose processor, the token having a sequence control information and a data to be processed.

9. 发明授权

US4901227A Microcomputer system 失效
标题翻译：微电脑系统
公开(公告)号：US4901227A
公开(公告)日：1990-02-13
申请号：US89871
申请日：1987-08-27
申请人： Masahiro Nomura , Yukio Maehashi
发明人： Masahiro Nomura , Yukio Maehashi
IPC分类号： G06F9/32 , G06F9/38 , G06F12/00 , G06F13/16 , G11C8/04
CPC分类号： G06F9/3802 , G06F9/321 , G11C8/04
摘要： A microcomputer system comprises a microprocessor and a memory chip which has on a single semiconductor substrate a pointer for indicating an address of an instruction code fetch destination, an incrementer for incrementing the pointer and a memory for storing programs and data. The microprocessor controls the update timing of the pointer in the memory chip, so that the instruction codes can be continuously read from the memory of the memory chip without outputting the addresses of the instruction code fetch destination from the microprocessor.
摘要翻译：微计算机系统包括微处理器和存储器芯片，其在单个半导体衬底上具有用于指示指令代码取出目的地的地址的指针，用于递增指针的增量器和用于存储程序和数据的存储器。微处理器控制存储器芯片中的指针的更新定时，从而可以从存储器芯片的存储器连续地读取指令代码，而不从微处理器输出指令代码取出目的地的地址。

10. 发明授权

US4860191A Coprocessor with dataflow circuitry controlling sequencing to execution unit of data received in tokens from master processor 失效
标题翻译：具有数据流电路的协处理器，其控制从主处理器的令牌中接收的数据的执行单元的排序
公开(公告)号：US4860191A
公开(公告)日：1989-08-22
申请号：US894535
申请日：1986-08-08
申请人： Masahiro Nomura , Yukio Maehashi
发明人： Masahiro Nomura , Yukio Maehashi
IPC分类号： G06F15/167 , G06F9/38 , G06F9/44 , G06F15/82
CPC分类号： G06F9/3889 , G06F9/3879 , G06F9/4436
摘要： An information processing apparatus with a dual processor system contains a general purpose processor for processing a required program and a special purpose processor for processing a specific operation in the required program. The special purpose processor is designed according to a data flow architecture and executes a task according to a token prepared by the general purpose processor, the token having sequence control information and data to be processed. The architecture employed enables placement of both the general purpose processor and the single purpose processor on a single semiconductor chip, and also enables asynchronous, parallel operation of the two processors.
摘要翻译：具有双处理器系统的信息处理装置包含用于处理所需程序的通用处理器和用于处理所需程序中的特定操作的专用处理器。专用处理器根据数据流架构进行设计，并根据由通用处理器准备的令牌执行任务，令牌具有序列控制信息和要处理的数据。所采用的架构使通用处理器和单用途处理器能够在单个半导体芯片上放置，并且还实现了两个处理器的异步并行操作。

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