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1. 发明授权

US4847867A Serial bus interface system for data communication using two-wire line as clock bus and data bus 失效
标题翻译：串行总线接口系统，用于使用双线线路作为时钟总线和数据总线的数据通信
公开(公告)号：US4847867A
公开(公告)日：1989-07-11
申请号：US91803
申请日：1987-09-01
申请人： Masaki Nasu , Shigetatsu Katori , Yukio Maehashi , Kazutoshi Yoshizawa
发明人： Masaki Nasu , Shigetatsu Katori , Yukio Maehashi , Kazutoshi Yoshizawa
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4077 , G06F13/4256
摘要： A serial data communication system is disclosed. This system includes a plurality of stations which are interconnected by a single clock wire and a single data wire. A master station in the stations includes a transistor push-pull circuit for driving the clock wire to output a clock signal on the clock wire. The clock signal thus has sharp leading and falling edges. The data wire is coupled to wire logic means. A transmitting station transmits each bit of a data signal on the data wire in synchronism with one of leading and falling edges of the associated clock pulse of the clock signal, and a receiving station receives each bit of the data signal in synchronism with the other of leading and falling edges of the associated clock pulse.
摘要翻译：公开了一种串行数据通信系统。该系统包括通过单个时钟线和单个数据线互连的多个站。站中的主站包括用于驱动时钟线的晶体管推挽电路，以在时钟线上输出时钟信号。因此，时钟信号具有尖锐的引导和下降沿。数据线耦合到线逻辑装置。发送站与时钟信号的相关联的时钟脉冲的前沿和下降沿中的一个同步地在数据线上传输数据信号的每一位，并且接收站与另一个的同步接收数据信号的每一位相关时钟脉冲的前沿和下降沿。

2. 发明授权

US5307470A Microcomputer having EEPROM provided with detector for detecting data write request issued before data write operation responsive to preceding data write request is completed 失效
标题翻译：完成具有EEPROM的微计算机，其具有用于检测响应于先前的数据写入请求的数据写入操作之前发出的数据写入请求的检测器
公开(公告)号：US5307470A
公开(公告)日：1994-04-26
申请号：US441739
申请日：1989-11-27
申请人： Toshiyuki Kataoka , Kazutoshi Yoshizawa
发明人： Toshiyuki Kataoka , Kazutoshi Yoshizawa
IPC分类号： G11C17/00 , G06F11/00 , G06F11/14 , G06F12/16 , G06F15/78 , G06F13/16 , G11C7/00
CPC分类号： G06F11/1415
摘要： A microcomputer includes a central processing unit (CPU) and an electrically erasable and programmable nonvolatile memory (EEPROM) fabricated on a single semiconductor chip. When CPU issues a data write request to EEPROM, a data write control circuit is initiated to perform a data write-processing in which data in an address of EEPROM selected by CPU is first erased and thereafter data from CPU is written into that selected address. There is further provided an over-written detection circuit for detecting that CPU issues another data write request to EEPROM while the data write control circuit is performing the data write-processing and for producing an over-write detection signal to CPU.
摘要翻译：微型计算机包括制造在单个半导体芯片上的中央处理单元（CPU）和电可擦除和可编程非易失性存储器（EEPROM）。当CPU向EEPROM发出数据写入请求时，启动数据写入控制电路以执行数据写入处理，其中首先擦除由CPU选择的EEPROM的地址中的数据，然后将来自CPU的数据写入该选择的地址。另外还提供了一种覆盖检测电路，用于检测CPU在数据写入控制电路正在执行数据写入处理并向CPU产生过写检测信号时向EEPROM发出另一个数据写入请求。

3. 发明授权

US5019966A Dual processors using busy signal for controlling transfer for predetermined length data when receiving processor is processing previously received data 失效
标题翻译：当接收处理器时，使用忙信号来控制预定长度数据的传输的双处理器正在处理先前接收到的数据
公开(公告)号：US5019966A
公开(公告)日：1991-05-28
申请号：US091813
申请日：1987-09-01
申请人： Sayuri Saito , Kazutoshi Yoshizawa , Yoshitaka Kitada
发明人： Sayuri Saito , Kazutoshi Yoshizawa , Yoshitaka Kitada
IPC分类号： G06F13/42 , G06F15/17
CPC分类号： G06F13/4256 , G06F15/17
摘要： A transmitting data processor comprises a data processing unit for supplying a predetermined length of data to be transferred and generating a transfer start signal, and a data transferring unit receiving the predetermined length of data to be transferred from the data processing unit and for transferring the predetermined length of data in a serial form to a receiving data processor. The transmitting data processor also includes a busy detector for detecting a busy signal from the receiving data processor, a register for temporarily holding the transfer start signal from the data processing unit, and a start controller associated to the data transferring unit for causing the data transferring unit to stop the transfer of data during the period the busy signal is active and for allowing the data transferring unit to start the transfer of data when the busy signal becomes inactive after the transfer start signal is generated.The receiving data processor includes a data receiving unit for receiving the predetermined length of data transferred from the transmitting data processor, and a data processing unit coupled to the receiving unit for processing the received data and generating a transfer acknowledge signal when it has completed the processing of the received data. The receiving data processor also includes a busy signal generator for generating the above mentioned busy signal in response to completion of reception of the predetermined length of data and making the busy signal inactive when the transfer acknowledge signal is generated.
摘要翻译：发送数据处理器包括：数据处理单元，用于提供要传输的预定长度的数据并生成传送开始信号;以及数据传送单元，从数据处理单元接收要传送的预定长度的数据，并传送预定的以串行形式将数据长度传送到接收数据处理器。发送数据处理器还包括用于检测来自接收数据处理器的忙信号的忙检测器，用于临时保存来自数据处理单元的传送开始信号的寄存器，以及与数据传送单元相关联的启动控制器，用于使数据传送在忙信号有效期间停止数据传送的单元，并且在生成传送开始信号之后，当忙信号变为无效时允许数据传送单元开始传输数据。接收数据处理器包括数据接收单元，用于接收从发送数据处理器传送的预定长度的数据;以及数据处理单元，耦合到接收单元，用于处理接收到的数据，并在其完成处理时产生传送确认信号的接收数据。接收数据处理器还包括忙信号发生器，用于响应于接收到预定长度的数据而完成上述忙信号，并且当生成传送确认信号时使忙信号无效。

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