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1. 发明授权

US08742804B2 Divider circuit and semiconductor device using the same 有权
标题翻译：分频电路和使用其的半导体器件
公开(公告)号：US08742804B2
公开(公告)日：2014-06-03
申请号：US13473658
申请日：2012-05-17
申请人： Masashi Fujita , Yukio Maehashi
发明人： Masashi Fujita , Yukio Maehashi
IPC分类号： H03B19/06
CPC分类号： H03K3/356156 , H03K21/023 , H03K23/44 , H03K23/52
摘要： A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided.
摘要翻译：提供具有低功耗和小面积的半导体器件。通过使用包括用于沟道的氧化物半导体的晶体管作为包括在触发器电路中的晶体管，可以实现晶体管数量少，功耗低，面积小的分压电路。通过使用分压电路，可以提供稳定运转且高可靠性的半导体装置。

2. 发明授权

US5287471A Data transfer controller using direct memory access method 失效
标题翻译：数据传输控制器采用直接存储器访问方式
公开(公告)号：US5287471A
公开(公告)日：1994-02-15
申请号：US556484
申请日：1990-07-24
申请人： Tsuyoshi Katayose , Yukio Maehashi
发明人： Tsuyoshi Katayose , Yukio Maehashi
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A data transfer controller for controlling DMA data transfer between a memory area and a peripheral unit. The data transfer controller has a first register which stores address information relative to a predetermined address of the memory area. A DMA control unit uses the first register and a second register to perform the DMA data transfer between the memory area and the peripheral unit. The data transfer controller also has a third register for storing data used for accessing the memory area of the DMA transfer. An updater is used to update the contents of the third register whenever a memory access uses the third register and is different from a memory access associated with data transfer between the memory area and the peripheral unit. Finally, a counter changes the contents of the third register in one direction whenever the data transfer between the memory area and the peripheral unit is performed. The counter changes the contents of the third register in an opposite direction whenever memory access using the third register is performed.
摘要翻译：一种数据传输控制器，用于控制存储区和外设之间的DMA数据传输。数据传输控制器具有第一寄存器，其存储相对于存储器区域的预定地址的地址信息。 DMA控制单元使用第一寄存器和第二寄存器来执行存储器区域和外围单元之间的DMA数据传输。数据传输控制器还具有用于存储用于访问DMA传输的存储区域的数据的第三寄存器。只要存储器访问使用第三寄存器并且与存储器区域和外围单元之间的数据传输相关联的存储器访问不同，更新器被用于更新第三寄存器的内容。最后，每当执行存储器区域和外围单元之间的数据传输时，计数器在一个方向上改变第三寄存器的内容。当执行使用第三个寄存器的存储器访问时，计数器以相反的方向改变第三寄存器的内容。

3. 发明授权

US4953082A Master processor providing tokens to dataflow processor for controlling instructions execution and data store operation 失效
标题翻译：主处理器为数据流处理器提供令牌，用于控制指令执行和数据存储操作
公开(公告)号：US4953082A
公开(公告)日：1990-08-28
申请号：US310577
申请日：1989-02-15
申请人： Masahiro Nomura , Yukio Maehashi
发明人： Masahiro Nomura , Yukio Maehashi
IPC分类号： G06F15/167 , G06F9/38 , G06F9/44 , G06F15/82
CPC分类号： G06F9/3889 , G06F9/3879 , G06F9/4436
摘要： An information processing apparatus with a dual processor system contains a general purpose processor for processing a required program and a special purpose processor for processing a specific operation in the required program. The special purpose processor is designed according to a data flow architecture and executes a task according to a token prepared by the general purpose processor, the token having a sequence control information and a data to be processed.

4. 发明授权

US4930068A Data processor having different interrupt processing modes 失效
标题翻译：数据处理器具有不同的中断处理模式
公开(公告)号：US4930068A
公开(公告)日：1990-05-29
申请号：US118671
申请日：1987-11-09
申请人： Tsuyoshi Katayose , Yukio Maehashi
发明人： Tsuyoshi Katayose , Yukio Maehashi
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A data processor comprises an interrupt processing request controller receiving processing requests from peripheral devices for generating an interrupt request. An execution unit has a first mode of executing the interrupt processing in accordance with a user's program and a second mode of executing the interrupt processing in accordance with a microprogram while maintaining an internal condition concerning execution of a program. The controller operates to selectively inhibit the execution of the interrupt processing in the first mode, but to basically allow the execution of the interrupt processing in the second mode.
摘要翻译：数据处理器包括接收来自外围设备的处理请求以产生中断请求的中断处理请求控制器。执行单元具有根据用户程序执行中断处理的第一模式和根据微程序执行中断处理的第二模式，同时保持关于程序执行的内部条件。控制器操作以选择性地禁止第一模式中的中断处理的执行，而基本上允许在第二模式中执行中断处理。

5. 发明授权

US4233665A Date data processor 失效
标题翻译：日期数据处理器
公开(公告)号：US4233665A
公开(公告)日：1980-11-11
申请号：US971129
申请日：1978-12-19
申请人： Yukio Maehashi , Hidetoshi Kosaka
发明人： Yukio Maehashi , Hidetoshi Kosaka
IPC分类号： G06F15/02 , G06F3/02 , G06F17/00 , G06F17/10 , G06F15/20
CPC分类号： G06Q10/109
摘要： A date data processor verifies whether an inputted date data exists or not. Inputted date data is stored in an input register which is composed of three sections according to month, day and year. A first calculating unit calculates the days difference between the inputted date data and a reference date, and the results are temporarily stored. A second calculating unit then performs an inverse calculating to arrive at a date based on the previously calculated days difference. The resulting date is compared with the inputted date to complete the verification.
摘要翻译：日期数据处理器验证输入的日期数据是否存在。输入日期数据存储在根据月，日，年三个部分组成的输入寄存器中。第一计算单元计算输入的日期数据和参考日期之间的日期差，并且暂时存储结果。第二计算单元然后基于先前计算的天差进行逆计算以达到日期。将结果日期与输入的日期进行比较以完成验证。

6. 发明授权

US4181861A Noise-inhibiting circuit responsive to a signal supplied only to the first stage of the circuit 失效
标题翻译：噪声抑制电路响应于仅提供给电路的第一级的信号
公开(公告)号：US4181861A
公开(公告)日：1980-01-01
申请号：US884398
申请日：1978-03-08
申请人： Yukio Maehashi
发明人： Yukio Maehashi
IPC分类号： G06F13/42 , G11C19/18 , G11C19/28 , H03K5/1252 , H03K5/135 , H03K19/0175 , H03K1/10
CPC分类号： G11C19/28 , G11C19/184 , H03K5/1252 , H03K5/135
摘要： A circuit for removing noise from an incoming input signal and for producing a noise free output signal in synchronism with a predetermined synchronization scheme. The memory signal is shifted through a plurality of series connected memory stages in sequence with first and second clock pulse sequences. The output signals of predetermined memory stages are compared and a noise free output signal is produced in response to stage output signals being simultaneously present at the output terminal of predetermined memory stages. The circuit does not utilize capacitors and resistors and is suitable for fabrication as an integrated circuit.
摘要翻译：一种用于从输入输入信号中去除噪声并与预定同步方案同步产生无噪声输出信号的电路。存储器信号按照与第一和第二时钟脉冲序列顺序移动通过多个串联连接的存储器级。比较预定存储器级的输出信号，并响应于同步存在于预定存储级的输出端的级输出信号产生无噪声输出信号。该电路不使用电容器和电阻器，并且适合作为集成电路制造。

7. 发明授权

US10079053B2 Memory element and memory device 有权
公开(公告)号：US10079053B2
公开(公告)日：2018-09-18
申请号：US13444177
申请日：2012-04-11
申请人： Takuro Ohmaru , Yukio Maehashi
发明人： Takuro Ohmaru , Yukio Maehashi
IPC分类号： G11C14/00 , G11C11/412
CPC分类号： G11C11/412 , G11C14/0054
摘要： An object is to provide a memory element having a novel structure where data can be held even after power supply is stopped. The memory element includes a latch circuit, a first selection circuit, a second selection circuit, a first nonvolatile memory circuit, and a second nonvolatile memory circuit. The first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor and a capacitor. The transistor included in each of the first nonvolatile memory circuit and the second nonvolatile memory circuit is a transistor in which a channel is formed in an oxide semiconductor film. The off-state current of such a transistor is extremely small. The transistor is turned off after data is input to a node where the transistor and the capacitor are connected to each other, and data can be held for a long time even after supply of power supply voltage is stopped.

8. 发明授权

US5159688A Information processor performing interrupt operation in two modes 失效
标题翻译：信息处理器在两种模式下执行中断操作
公开(公告)号：US5159688A
公开(公告)日：1992-10-27
申请号：US691284
申请日：1991-04-25
申请人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
发明人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
IPC分类号： G06F13/32
CPC分类号： G06F13/32
摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

9. 发明授权

US4964141A Serial data processor capable of transferring data at a high speed 失效
标题翻译：能够高速传输数据的串行数据处理器
公开(公告)号：US4964141A
公开(公告)日：1990-10-16
申请号：US182006
申请日：1988-04-15
申请人： Osamu Matsushima , Yukio Maehashi
发明人： Osamu Matsushima , Yukio Maehashi
IPC分类号： G06F13/38 , G06F13/00 , H04L1/16 , H04L5/16 , H04L7/00 , H04L7/04 , H04L29/08
CPC分类号： H04L7/0008 , H04L5/16 , H04L1/1692
摘要： A serial data processor is coupled to a single data line and a single clock line for serial data transfer in synchronism with a clock signal. The data processor comprises a shift register coupled to the serial data line and operated to serially output the data in synchronism with a clock on the clock line, and an output buffer connected to receive the data serially outputted from the shift register and coupled to sequentially output the received data to the data line. This output buffer includes a push-pull driver having an output connected to the data line and an input driven by the data serially outputted from the shift register. A clock counter is coupled to receive the clock on the clock line so as to maintain the push-pull driver in an operable condition until the count value reaches a predetermined value and to bring the output of the push-pull driver into a floating condition after the count value reached a predetermined value. There is provided a data line control circuit coupled to the data line and controlled by the clock counter to bring the data line to a high level after the count value of the clock counter reaches the predetermined value.

10. 发明授权

US08724407B2 Signal processing circuit 有权
标题翻译：信号处理电路
公开(公告)号：US08724407B2
公开(公告)日：2014-05-13
申请号：US13428015
申请日：2012-03-23
申请人： Hidetomo Kobayashi , Yukio Maehashi
发明人： Hidetomo Kobayashi , Yukio Maehashi
IPC分类号： G11C7/10
CPC分类号： G11C11/4074 , G11C7/1006 , G11C11/407 , G11C2207/2227
摘要： To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.
摘要翻译：为了提供包括具有新颖结构的非易失性存储器电路的信号处理电路，信号处理电路包括用于控制运算部分和存储器的运算部分，存储器和控制部分。控制部分包括一组易失性存储器电路和用于存储在易失性存储器电路中的数据的第一非易失性存储器电路，存储器包括多个第二非易失性存储器电路，以及第一非易失性存储器电路和第二非易失性存储器电路每个都包括在氧化物半导体层中具有通道的晶体管和一个电容器，其中一对电极中的一个电极电连接到当晶体管截止时被设置为浮置状态的节点。

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