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1. 发明授权

US07042206B2 Integrated circuit and method for operating the integrated circuit 失效
公开(公告)号：US07042206B2
公开(公告)日：2006-05-09
申请号：US10245629
申请日：2002-09-17
申请人： Oliver Kiehl , Hermann Ruckerbauer
发明人： Oliver Kiehl , Hermann Ruckerbauer
IPC分类号： G01R23/175 , H04L1/22
CPC分类号： G11C29/022 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012 , H04L1/205
摘要： An integrated circuit has connecting pads for outputting digital signals, a connection for a time reference signal, and an assessment circuit to measure and assess a phase shift between one of the digital signals and the time reference signal. A receiver circuit is connected to a respective junction between one of the connecting pads and an associated output driver. A device for matching propagation times of signals applied to the receiver circuit is provided. The assessment circuit is connected to the receiver circuit and has an output to output a measured result. In each case, the phase shift of the signals to be output in relation to the time reference signal is measured and assessed separately. An offset of the switching edges of the signals to be output can be determined relatively accurately and corrected.

2. 发明授权

US06765826B2 Write protection control for electronic assemblies 失效
标题翻译：写入电子组件的保护控制
公开(公告)号：US06765826B2
公开(公告)日：2004-07-20
申请号：US10226684
申请日：2002-08-23
申请人： Oliver Kiehl , Hermann Ruckerbauer
发明人： Oliver Kiehl , Hermann Ruckerbauer
IPC分类号： G11C1604
CPC分类号： G11C16/22 , G06F12/1433
摘要： The invention relates to an electronic assembly having a non-volatile memory device with a controllable write protection feature and a switching configuration for generating a write protection signal from potentials at the supply terminals of the electronic assembly.
摘要翻译：本发明涉及具有可写写保护特征的非易失性存储器件和用于从电子组件的电源端的电位产生写保护信号的开关配置的电子组件。

3. 发明授权

US07831797B2 Memory system and method for transferring data therein 有权
标题翻译：用于在其中传输数据的存储器系统和方法
公开(公告)号：US07831797B2
公开(公告)日：2010-11-09
申请号：US11862915
申请日：2007-09-27
申请人： Hermann Ruckerbauer
发明人： Hermann Ruckerbauer
IPC分类号： G06F12/00
CPC分类号： G11C7/1018 , G06F13/1684
摘要： A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.
摘要翻译：存储器系统在功能上被设计成使得尽管在没有纠错装置的情况下进行操作，但实际提供用于纠错的存储器模块的存储器芯片被同时用于数据传输。控制装置被配置为接收，存储和传送数据分组到第一和第二组存储器芯片。将内部分组数据从控制设备传送到存储器进行，使得第一记录被存储在第二组存储器芯片中，并且附加记录被存储在第一组存储器芯片中。在优选实施例中，在第二组存储器芯片中分配数据，使得与传送到第一组存储器芯片相比，至少一个额外的转移步骤发生到第二组存储器芯片。在附加传送步骤中，第一组存储器芯片被从接收数据中被掩蔽。

4. 发明授权

US07768857B2 Method of refreshing data in a storage location based on heat dissipation level and system thereof 有权
标题翻译：基于散热水平及其系统刷新存储位置中的数据的方法
公开(公告)号：US07768857B2
公开(公告)日：2010-08-03
申请号：US11949639
申请日：2007-12-03
申请人： Hermann Ruckerbauer
发明人： Hermann Ruckerbauer
IPC分类号： G11C7/04
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40626 , G11C2211/4061
摘要： An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data is repeatedly refreshed with a second predetermined refresh rate.
摘要翻译：一种包括存储位置的集成设备，其中存储在所述存储位置中的数据在第一时间段期间以第一预定刷新率重复地刷新。第一时间段提供第一预定持续时间。在第一时间段结束之后，数据以第二预定刷新率反复刷新。

5. 发明申请

US20100077157A1 MULTI MASTER DRAM ARCHITECTURE 有权
标题翻译：多主体DRAM架构
公开(公告)号：US20100077157A1
公开(公告)日：2010-03-25
申请号：US12235063
申请日：2008-09-22
申请人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
发明人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
IPC分类号： G06F12/00 , G06F13/14
CPC分类号： G06F13/1605 , G06F13/1684 , Y02D10/14
摘要： Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, the memory device may be a package comprising a plurality of stacked memory dies.
摘要翻译：本发明的实施例提供一种存储器件，其可以经由存储器件的相应端口被多个控制器或处理器核存取。每个控制器可以经由数据总线耦合到存储器设备的相应端口。存储器设备的每个端口可以与存储器的预定义部分相关联，从而使每个控制器访问不同部分的存储器，而不受其他控制器的干扰。公共命令/地址总线可以将多个控制器耦合到存储器设备。每个控制器可以在存储器访问控制总线上断言有效信号以获得对命令/地址总线的访问以启动存储器访问。在一些实施例中，存储器件可以是包括多个堆叠的存储器管芯的封装。

6. 发明申请

US20100046266A1 High Speed Memory Architecture 有权
标题翻译：高速内存架构
公开(公告)号：US20100046266A1
公开(公告)日：2010-02-25
申请号：US12194414
申请日：2008-08-19
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
IPC分类号： G11C5/02 , G11C7/00 , G11C8/18 , H01L23/52 , H01L21/00
CPC分类号： G11C11/4097 , G11C5/025 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.
摘要翻译：公开了存储器件和存储器模块。在一个实施例中，存储器件包括具有第一边缘和与第一边缘相对的第二边缘的半导体衬底。多个存储体设置在半导体衬底的中心部分，每个存储体包括多个存储单元。多个输入/输出触点设置在第一边缘和存储体之间。延迟锁定环电路设置在第一边缘附近。多个地址和命令触点设置在第二边缘和存储体之间。

7. 发明申请

US20100032820A1 Stacked Memory Module 审中-公开
标题翻译：堆叠内存模块
公开(公告)号：US20100032820A1
公开(公告)日：2010-02-11
申请号：US12187183
申请日：2008-08-06
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
IPC分类号： H01L23/52 , H01L21/00 , H05K7/00
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/49811 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/18 , H01L2224/0554 , H01L2224/05554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2924/00014 , H01L2924/01055 , H01L2924/14 , H01L2924/3011 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/0555 , H01L2224/0556
摘要： Memory modules, computing systems, and methods of manufacturing memory modules are disclosed. In one embodiment, a memory module includes a substrate having a first side and a second side opposed to the first side. A plurality of pins is disposed on the first side of the substrate. A first plurality of memory chips are arranged in a first chip layer, the first chip layer overlying the second side of the substrate. Electrical contacts of the first plurality of memory chips are electrically coupled to the pins. A second plurality of memory chips is arranged in a second chip layer, the second chip layer overlying the first chip layer. Electrical contacts of the second plurality of memory chips are electrically coupled to the pins.
摘要翻译：公开了内存模块，计算系统和制造内存模块的方法。在一个实施例中，存储器模块包括具有与第一侧相对的第一侧和第二侧的衬底。多个引脚设置在基板的第一侧上。第一多个存储器芯片布置在第一芯片层中，第一芯片层覆盖在基板的第二侧。第一多个存储器芯片的电触点电连接到引脚。第二多个存储器芯片被布置在第二芯片层中，第二芯片层覆盖第一芯片层。第二多个存储器芯片的电触点电连接到引脚。

8. 发明申请

US20090267084A1 Integrated circuit with wireless connection 有权
标题翻译：集成电路与无线连接
公开(公告)号：US20090267084A1
公开(公告)日：2009-10-29
申请号：US12109558
申请日：2008-04-25
申请人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
发明人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
IPC分类号： H01L33/00 , H01L29/00 , H01L21/60
CPC分类号： H01L23/48 , H01L25/0657 , H01L25/167 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/32145 , H01L2225/06527 , H01L2924/00014 , H01L2924/01019 , H01L2224/05599
摘要： An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.
摘要翻译：集成电路包括：器件堆叠，其包括：具有第一无线耦合元件的存储器件，以及具有第二无线耦合元件的半导体器件。第一和第二无线耦合元件面对面布置并且被配置为在存储器件和半导体器件之间提供无线连接。

9. 发明授权

US07560807B2 Arrangement of semiconductor memory devices and semiconductor memory module comprising an arrangement of semiconductor memory devices 失效
标题翻译：包括半导体存储器件的布置的半导体存储器件和半导体存储器模块的布置
公开(公告)号：US07560807B2
公开(公告)日：2009-07-14
申请号：US11638310
申请日：2006-12-12
申请人： Hermann Ruckerbauer , Holger Schroeter
发明人： Hermann Ruckerbauer , Holger Schroeter
IPC分类号： H01L23/02
CPC分类号： H01L25/105 , H01L23/5387 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06555 , H01L2225/06575 , H01L2225/06579 , H01L2225/107 , H01L2924/15192
摘要： An arrangement of semiconductor memory devices includes a first semiconductor memory device and a second semiconductor memory device. The arrangement of semiconductor memory devices also has a flexible substrate. A first electrically conductive conductor track is arranged in the flexible substrate. At least one first contact of the flexible substrate is coupled to the at least one second contact of the second semiconductor memory device through the first electrically conductive conductor track. A second electrically conductive conductor track is arranged in the flexible substrate.
摘要翻译：半导体存储器件的布置包括第一半导体存储器件和第二半导体存储器件。半导体存储器件的布置也具有柔性衬底。第一导电导体轨道布置在柔性基板中。柔性基板的至少一个第一接触件通过第一导电导体轨道耦合到第二半导体存储器件的至少一个第二接触件。第二导电导体轨道布置在柔性基板中。

10. 发明授权

US07414917B2 Re-driving CAwD and rD signal lines 失效
标题翻译：重新启动CAwD和rD信号线
公开(公告)号：US07414917B2
公开(公告)日：2008-08-19
申请号：US11192335
申请日：2005-07-29
申请人： Hermann Ruckerbauer , Simon Muff , Christian Weiss , Peter Gregorius
发明人： Hermann Ruckerbauer , Simon Muff , Christian Weiss , Peter Gregorius
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/06 , H05K1/142
摘要： Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.
摘要翻译：本文描述了使用其的半导体存储器模块和半导体存储器系统。这些模块将常规DIMM分成一系列独立的较小内存模块。每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。

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