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1. 发明申请

US20110258501A1 METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION 有权
标题翻译：低密码扫描压缩的方法和装置
公开(公告)号：US20110258501A1
公开(公告)日：2011-10-20
申请号：US13172046
申请日：2011-06-29
申请人： Nur A. TOUBA , Laung-Terng WANG , Zhigang JIANG , Shianling WU , Jiangping YAN
发明人： Nur A. TOUBA , Laung-Terng WANG , Zhigang JIANG , Shianling WU , Jiangping YAN
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

2. 发明申请

US20120173940A1 ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS 有权
标题翻译：用于保护软件错误的稳健扫描合成
公开(公告)号：US20120173940A1
公开(公告)日：2012-07-05
申请号：US13416529
申请日：2012-03-09
申请人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
发明人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：用于在用于在系统中生成鲁棒扫描设计的设计上进行软错误保护的鲁棒扫描合成的方法在寄存器传送级（RTL）或门级选择性地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

3. 发明申请

US20110022908A1 ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS 有权
标题翻译：用于保护软件错误的稳健扫描合成
公开(公告)号：US20110022908A1
公开(公告)日：2011-01-27
申请号：US12508977
申请日：2009-07-24
申请人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
发明人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：一种用于在用于在系统中生成鲁棒扫描设计的设计上执行用于软错误保护的鲁棒扫描合成的方法。系统在寄存器传输级（RTL）或门级有选择地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

4. 发明申请

US20140143623A1 METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION 审中-公开
标题翻译：低密码扫描压缩的方法和装置
公开(公告)号：US20140143623A1
公开(公告)日：2014-05-22
申请号：US13681968
申请日：2012-11-20
申请人： Nur A. TOUBA , Laung-Terng WANG , Shianling WU
发明人： Nur A. TOUBA , Laung-Terng WANG , Shianling WU
IPC分类号： G01R31/3177
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

5. 发明申请

US20110022909A1 APPARATUS AND METHOD FOR PROTECTING SOFT ERRORS 有权
标题翻译：用于保护软错误的装置和方法
公开(公告)号：US20110022909A1
公开(公告)日：2011-01-27
申请号：US12509019
申请日：2009-07-24
申请人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang
发明人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang
IPC分类号： G01R31/3177 , G06F11/07 , G06F11/25
CPC分类号： G01R31/31816 , G01R31/318544 , G06F17/505 , G06F2217/14
摘要： An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.
摘要翻译：用于进行制造测试操作，慢速快照操作，慢速签名分析操作，速度特征分析操作，缺陷容差操作或缺陷容错操作的能力的软错误恢复或校正的装置和方法以上操作的任意组合。在一个实施例中，一种装置包括用于软错误弹性的系统电路，阴影电路和输出接合电路。耦合到系统电路和阴影电路的输出端子的输出接合电路至少包括用于缺陷容限的S元件。在另一个实施例中，一种装置包括系统电路，阴影电路，调试电路和用于软错误校正的输出连接电路。耦合到系统电路，阴影电路和调试电路的输出端子的输出接合电路至少包括用于缺陷容差的V元件。

6. 发明申请

US20100138709A1 METHOD AND APPARATUS FOR DELAY FAULT COVERAGE ENHANCEMENT 审中-公开
标题翻译：延迟故障覆盖增强的方法和装置
公开(公告)号：US20100138709A1
公开(公告)日：2010-06-03
申请号：US12554437
申请日：2009-09-04
申请人： Laung-Terng WANG , Michael S. Hsiao , Hao-Jan Chao , Zhigang Jiang , Shianling Wu , Jianping Yan
发明人： Laung-Terng WANG , Michael S. Hsiao , Hao-Jan Chao , Zhigang Jiang , Shianling Wu , Jianping Yan
IPC分类号： G01R31/3177 , G06F11/27
CPC分类号： G01R31/318552
摘要： A hybrid clocking scheme for simultaneously detecting a b-cycle path-delay fault in a b-cycle (false) path and a c-cycle path-delay fault in a c-cycle (false) path using at least n+1 at-speed clock pulses during a capture operation in a clock domain in a scan design or a scan-based BIST design, where 1
摘要翻译：一种用于同时检测b周期（假）路径中的b周期路径延迟故障和c周期（假）路径中的c周期路径延迟故障的混合时钟方案，其使用至少n + 1 at- 在扫描设计或基于扫描的BIST设计中的时钟域中的捕获操作期间，速度时钟脉冲，其中1 <= b <= c <= n。扫描设计或BIST设计包括多个扫描链，每个扫描链包括串联耦合的多个扫描单元。该设计包括一个或多个时钟域，每个时钟域以其预期的工作频率或速度运行。混合时钟方案包括至少一个速率移位时钟脉冲或一个在速捕获时钟脉冲，紧接着在捕获操作期间至少两个速度捕捉时钟脉冲，以同时检测b周期路径延迟故障，以及时钟域内的c循环路径延迟故障。

7. 发明申请

US20100287430A1 MULTIPLE-CAPTURE DFT SYSTEM TO REDUCE PEAK CAPTURE POWER DURING SELF-TEST OR SCAN TEST 失效
标题翻译：多重捕获DFT系统在自检或扫描测试期间减少峰值捕获功率
公开(公告)号：US20100287430A1
公开(公告)日：2010-11-11
申请号：US12797302
申请日：2010-06-09
申请人： Laung-Terng WANG , Shianling Wu , Zhigang Jiang , Jinsong Liu , Hao-Jan Chao , Lizhen Yu , Feifei Zhao , Fangfang Li , Jianping Yan
发明人： Laung-Terng WANG , Shianling Wu , Zhigang Jiang , Jinsong Liu , Hao-Jan Chao , Lizhen Yu , Feifei Zhao , Fangfang Li , Jianping Yan
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/31704 , G01R31/318552 , G01R31/318594
摘要： A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
摘要翻译：一种用于提供有序捕获时钟的方法，用于检测或定位N个时钟域内的故障，以及在扫描测试或自检模式下跨过集成电路或电路组件中的任何两个时钟域的故障，其中N> 1，每个时钟域具有一个捕获时钟和多个扫描单元，每个捕获时钟包括多个捕获时钟脉冲; 所述方法包括：（a）在移入操作期间，在所述集成电路或电路组件中的所述N个时钟域内产生和移入N个测试刺激; （b）将所述捕获时钟的有序序列应用于所述N个时钟域内的所有所述扫描单元，所述捕获时钟的有序序列包括至少多个捕获时钟脉冲，所述捕获时钟脉冲以两个或更多个选定的捕获时钟以顺序排列，使得在捕获操作期间，所有时钟域不会同时触发; 和（c）分析所有所述扫描单元的输出响应以定位其中的任何故障。

8. 发明申请

US20120166903A1 MULTIPLE-CAPTURE DFT SYSTEM TO REDUCE PEAK CAPTURE POWER DURING SELF-TEST OR SCAN TEST 失效
标题翻译：多重捕获DFT系统在自检或扫描测试期间减少峰值捕获功率
公开(公告)号：US20120166903A1
公开(公告)日：2012-06-28
申请号：US13309987
申请日：2011-12-02
申请人： Laung-Terng WANG , Hao-Jan CHAO , Shianling WU
发明人： Laung-Terng WANG , Hao-Jan CHAO , Shianling WU
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/31704 , G01R31/318552 , G01R31/318594
摘要： A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, includes the steps of: (a) generating and shifting-in N test stimuli to all scan cells within the N clock domains during a shift-in operation; (b) applying an ordered sequence of capture clocks to all scan cells within the N clock domains, the ordered sequence of capture clocks including a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all scan cells to locate any faults therein.
摘要翻译：一种用于提供有序捕获时钟的方法，用于检测或定位N个时钟域内的故障，以及跨过扫描测试或自检模式中的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1，包括以下步骤：（a）在移入操作期间，在N个时钟域内产生和移动N个测试刺激到所有扫描单元; （b）将有序的捕获时钟序列应用于N个时钟域内的所有扫描单元，所述捕获时钟的有序序列包括来自两个或更多个选定的捕获时钟的多个捕获时钟脉冲，其以顺序排列，使得所有时钟域在捕获操作期间不会同时触发; 和（c）分析所有扫描单元的输出响应以定位其中的任何故障。

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