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1. 发明授权

US08091002B2 Multiple-capture DFT system to reduce peak capture power during self-test or scan test 失效
标题翻译：多捕捉DFT系统，可在自检或扫描测试期间降低峰值捕获能力
公开(公告)号：US08091002B2
公开(公告)日：2012-01-03
申请号：US12797302
申请日：2010-06-09
申请人： Laung-Terng Wang , Shianling Wu , Zhigang Jiang , Jinsong Liu , Hao-Jan Chao , Lizhen Yu , Feifei Zhao , Fangfang Li , Jianping Yan
发明人： Laung-Terng Wang , Shianling Wu , Zhigang Jiang , Jinsong Liu , Hao-Jan Chao , Lizhen Yu , Feifei Zhao , Fangfang Li , Jianping Yan
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/31704 , G01R31/318552 , G01R31/318594
摘要： A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
摘要翻译：一种用于提供有序捕获时钟的方法，用于检测或定位N个时钟域内的故障，以及在扫描测试或自检模式下跨过集成电路或电路组件中的任何两个时钟域的故障，其中N> 1，每个时钟域具有一个捕获时钟和多个扫描单元，每个捕获时钟包括多个捕获时钟脉冲; 所述方法包括：（a）在移入操作期间，在所述集成电路或电路组件中的所述N个时钟域内产生和移入N个测试刺激; （b）将所述捕获时钟的有序序列应用于所述N个时钟域内的所有所述扫描单元，所述捕获时钟的有序序列包括至少多个捕获时钟脉冲，所述捕获时钟脉冲以两个或更多个选定的捕获时钟以顺序排列，使得在捕获操作期间，所有时钟域不会同时触发; 和（c）分析所有所述扫描单元的输出响应以定位其中的任何故障。

2. 发明申请

US20100287430A1 MULTIPLE-CAPTURE DFT SYSTEM TO REDUCE PEAK CAPTURE POWER DURING SELF-TEST OR SCAN TEST 失效
标题翻译：多重捕获DFT系统在自检或扫描测试期间减少峰值捕获功率
公开(公告)号：US20100287430A1
公开(公告)日：2010-11-11
申请号：US12797302
申请日：2010-06-09
申请人： Laung-Terng WANG , Shianling Wu , Zhigang Jiang , Jinsong Liu , Hao-Jan Chao , Lizhen Yu , Feifei Zhao , Fangfang Li , Jianping Yan
发明人： Laung-Terng WANG , Shianling Wu , Zhigang Jiang , Jinsong Liu , Hao-Jan Chao , Lizhen Yu , Feifei Zhao , Fangfang Li , Jianping Yan
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/31704 , G01R31/318552 , G01R31/318594
摘要： A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
摘要翻译：一种用于提供有序捕获时钟的方法，用于检测或定位N个时钟域内的故障，以及在扫描测试或自检模式下跨过集成电路或电路组件中的任何两个时钟域的故障，其中N> 1，每个时钟域具有一个捕获时钟和多个扫描单元，每个捕获时钟包括多个捕获时钟脉冲; 所述方法包括：（a）在移入操作期间，在所述集成电路或电路组件中的所述N个时钟域内产生和移入N个测试刺激; （b）将所述捕获时钟的有序序列应用于所述N个时钟域内的所有所述扫描单元，所述捕获时钟的有序序列包括至少多个捕获时钟脉冲，所述捕获时钟脉冲以两个或更多个选定的捕获时钟以顺序排列，使得在捕获操作期间，所有时钟域不会同时触发; 和（c）分析所有所述扫描单元的输出响应以定位其中的任何故障。

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