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1. 发明申请

US20110258501A1 METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION 有权
标题翻译：低密码扫描压缩的方法和装置
公开(公告)号：US20110258501A1
公开(公告)日：2011-10-20
申请号：US13172046
申请日：2011-06-29
申请人： Nur A. TOUBA , Laung-Terng WANG , Zhigang JIANG , Shianling WU , Jiangping YAN
发明人： Nur A. TOUBA , Laung-Terng WANG , Zhigang JIANG , Shianling WU , Jiangping YAN
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

2. 发明申请

US20110047426A1 METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION 有权
标题翻译：低密码扫描压缩的方法和装置
公开(公告)号：US20110047426A1
公开(公告)日：2011-02-24
申请号：US12546060
申请日：2009-08-24
申请人： Nur A. TOUBA , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
发明人： Nur A. TOUBA , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述_combinational逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个所选故障的压缩扫描模式。

3. 发明授权

US07783940B2 Apparatus for redundancy reconfiguration of faculty memories 有权
标题翻译：用于冗余重新配置教师记忆的装置
公开(公告)号：US07783940B2
公开(公告)日：2010-08-24
申请号：US12155596
申请日：2008-06-06
申请人： Lizhen Yu , Shianling Wu , Zhigang Jiang , Laung-Terng Wang
发明人： Lizhen Yu , Shianling Wu , Zhigang Jiang , Laung-Terng Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/808
摘要： A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN−1) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXi each having k+1 input signals from k redundant blocks (R0 to Rk−1) and one base block (Ni), capable of being connected to N output signals (qi); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.
摘要翻译：与k个冗余块相关联的N个基本块的存储器冗余重新配置。如果基块有故障，数据将被写入基块和无缺陷冗余块; k复用器MUXRi，每个具有能够连接到冗余块的k个输入信号的N个输入信号（d0至dN-1）; N个多路复用器MUXi，其具有能够连接到N个输出信号（qi）的来自k个冗余块（R0至RK-1）和一个基本块（Ni）的k + 1个输入信号; 以及与每个多路复用器相关联的逻辑装置，以将多路复用器的输入信号转换成其输出信号。

4. 发明申请

US20060242502A1 Method and apparatus for broadcasting scan patterns in a random access scan based integrated circuit 有权
标题翻译：用于在基于随机存取扫描的集成电路中广播扫描图案的方法和装置
公开(公告)号：US20060242502A1
公开(公告)日：2006-10-26
申请号：US11348519
申请日：2006-02-07
申请人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
发明人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318533 , G01R31/318591 , G01R31/31926
摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit. The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.
摘要翻译：用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。虚拟扫描控制器控制广播机构的操作。系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。进一步提出了方法来重新排列所选择的扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。所使用的扫描结构也可以是基于随机存取扫描的集成电路，其中集成电路包括随机访问扫描（RAS）阵列，其随机且唯一可寻址。在随机存取扫描中，可以通过选择性地更新RAS细胞来应用测试模式，并且可以通过直接读出过程来观察测试响应。消除串行扫描固有的移位过程，随机访问扫描产生比串行扫描低得多的测试功耗。

5. 发明授权

US07945833B1 Method and apparatus for pipelined scan compression 有权
标题翻译：流水线扫描压缩方法和装置
公开(公告)号：US07945833B1
公开(公告)日：2011-05-17
申请号：US11889710
申请日：2007-08-15
申请人： Laung-Terng (L.-T.) Wang , Nur A. Touba , Boryau (Jack) Sheu , Shianling Wu , Zhigang Jiang
发明人： Laung-Terng (L.-T.) Wang , Nur A. Touba , Boryau (Jack) Sheu , Shianling Wu , Zhigang Jiang
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318547
摘要： A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于在基于扫描的集成电路中减少测试数据量和测试应用时间的流水线扫描压缩方法和装置，而不降低扫描测试模式或自检模式下扫描链操作的速度。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括一个解压缩器，它包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。解压缩器在其压缩的扫描输入端解压缩压缩的扫描图案，并将解压缩器的输出端上产生的解压缩扫描图案驱动到基于扫描的集成电路的扫描数据输入端。由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

6. 发明申请

US20090303815A1 Apparatus for redundancy reconfiguration of faculty memories 有权
标题翻译：用于冗余重新配置教师记忆的装置
公开(公告)号：US20090303815A1
公开(公告)日：2009-12-10
申请号：US12155596
申请日：2008-06-06
申请人： Lizhen Yu , Shianling Wu , Zhigang Jiang , Laung-Terng Wang
发明人： Lizhen Yu , Shianling Wu , Zhigang Jiang , Laung-Terng Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/808
摘要： A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN−1) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXi each having k+1 input signals from k redundant blocks (R0 to Rk−1) and one base block (Ni), capable of being connected to N output signals (qi); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.
摘要翻译：与k个冗余块相关联的N个基本块的存储器冗余重新配置。如果基块有故障，数据将被写入基块和无缺陷冗余块; k复用器MUXRi，每个具有能够连接到冗余块的k个输入信号的N个输入信号（d0至dN-1）; N个多路复用器MUXi，其具有能够连接到N个输出信号（qi）的来自k个冗余块（R0至RK-1）和一个基本块（Ni）的k + 1个输入信号; 以及与每个多路复用器相关联的逻辑装置，以将多路复用器的输入信号转换成其输出信号。

7. 发明授权

US07512851B2 Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit 有权
标题翻译：用于在基于扫描的集成电路中移动高速扫描图案的方法和装置
公开(公告)号：US07512851B2
公开(公告)日：2009-03-31
申请号：US10901298
申请日：2004-07-29
申请人： Laung-Terng Wang , Khader S. Abdel-Hafez , Xiaoqing Wen , Boryau (Jack) Sheu , Fei-Sheng Hsu , Augusli Kifli , Shyh-Horng Lin , Shianling Wu , Shun-Miin (Sam) Wang , Ming-Tung Chang
发明人： Laung-Terng Wang , Khader S. Abdel-Hafez , Xiaoqing Wen , Boryau (Jack) Sheu , Fei-Sheng Hsu , Augusli Kifli , Shyh-Horng Lin , Shianling Wu , Shun-Miin (Sam) Wang , Ming-Tung Chang
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318335 , G01R31/318547 , G01R31/318572 , G01R31/31905
摘要： A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.
摘要翻译：一种方法和装置将以所选择的数据速率R1提供的压缩输入激励时分解复用和解压缩为以所选择的数据速率R2驱动的解压缩的激励，以驱动基于扫描的集成电路中的选定的扫描链，使用多个的时分解复用器和时分复用器，用于将刺激和测试响应移入和移出高速I / O焊盘，以减少测试时间，测试成本和扫描引脚数。还提出了一种用于合成时分复用器，解压缩器，压缩器和时分复用器的合成方法。

8. 发明申请

US20080276143A1 Method and apparatus for broadcasting scan patterns in a random access based integrated circuit 有权
标题翻译：用于在基于随机接入的集成电路中广播扫描模式的方法和装置
公开(公告)号：US20080276143A1
公开(公告)日：2008-11-06
申请号：US12216640
申请日：2008-07-09
申请人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
发明人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547 , G01R31/318533 , G01R31/318591 , G01R31/31926
摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.
摘要翻译：用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。虚拟扫描控制器控制广播机构的操作。系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。进一步提出了方法来重新排列所选择的扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。所使用的扫描结构也可以是基于随机存取扫描的集成电路，其中集成电路包括随机访问扫描（RAS）阵列，其随机且唯一可寻址。在随机存取扫描中，可以通过选择性地更新RAS细胞来应用测试模式，并且可以通过直接读出过程来观察测试响应。消除串行扫描固有的移位过程，随机访问扫描产生比串行扫描低得多的测试功耗。

9. 发明授权

US07412637B2 Method and apparatus for broadcasting test patterns in a scan based integrated circuit 有权
标题翻译：用于在基于扫描的集成电路中广播测试模式的方法和装置
公开(公告)号：US07412637B2
公开(公告)日：2008-08-12
申请号：US11348519
申请日：2006-02-07
申请人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
发明人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318533 , G01R31/318591 , G01R31/31926
摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.
摘要翻译：用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。虚拟扫描控制器控制广播机构的操作。系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。进一步提出了方法来重新排列所选择的扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。所使用的扫描结构也可以是基于随机存取扫描的集成电路，其中集成电路包括随机访问扫描（RAS）阵列，其随机且唯一可寻址。在随机存取扫描中，可以通过选择性地更新RAS细胞来应用测试模式，并且可以通过直接读出过程来观察测试响应。消除串行扫描固有的移位过程，随机访问扫描产生比串行扫描低得多的测试功耗。

10. 发明授权

US6052808A Maintenance registers with Boundary Scan interface 失效
标题翻译：带边界扫描界面的维护寄存器
公开(公告)号：US6052808A
公开(公告)日：2000-04-18
申请号：US962340
申请日：1997-10-31
申请人： Shianling Wu , Ramesh Karri , Charles E. Stroud
发明人： Shianling Wu , Ramesh Karri , Charles E. Stroud
IPC分类号： G01R31/3185 , G01R31/28 , H02H3/05
CPC分类号： G01R31/318569
摘要： Concurrent Fault Detector Circuits (CFDCs) are test components of a main system, e.g. an Application Specific Integrated Circuit, and provide the results of the tests in parallel to at least one Error Source Register (ESR). Instead of reading out the ESR in parallel, its contents are copied to a serial shadow register so the contents can be read out in series to an error correcting application, thus reducing the number of output pins and the burden on resources of the main system. The ESR's receipt and transfer of information is under the control of a Boundary Scan Interface. In one embodiment, the test results are prioritized and compared to data in a mask register so that only important errors create a system interrupt which causes the read out of data from the shadow register.
摘要翻译：并发故障检测器电路（CFDC）是主系统的测试组件，例如专用集成电路，并且将测试结果与至少一个错误源寄存器（ESR）并行提供。不是并行读出ESR，而是将其内容复制到串行影子寄存器，以便可以将内容串行读出到纠错应用程序，从而减少输出引脚数量和主系统资源负担。 ESR的收据和信息传输受边界扫描界面的控制。在一个实施例中，测试结果被优先化并与掩码寄存器中的数据进行比较，使得只有重要的错误产生导致从影子寄存器读出数据的系统中断。

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