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1. 发明授权

US5222215A CPU expansive gradation of I/O interruption subclass recognition 失效
标题翻译： CPU扩展I / O中断SUBCLASS识别
公开(公告)号：US5222215A
公开(公告)日：1993-06-22
申请号：US752149
申请日：1991-08-29
申请人： Norman C. Chou , Peter H. Gum , Roger E. Hough , Moon J. Kim , James C. Mazurowski , Donald W. McCauley , Casper A. Scalzi , John F. Scanlon , Leslie W. Wyman
发明人： Norman C. Chou , Peter H. Gum , Roger E. Hough , Moon J. Kim , James C. Mazurowski , Donald W. McCauley , Casper A. Scalzi , John F. Scanlon , Leslie W. Wyman
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4812
摘要： A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

2. 发明授权

US5461721A System for transferring data between I/O devices and main or expanded storage under dynamic control of independent indirect address words (IDAWs) 失效
标题翻译：用于在独立间接地址字（IDAW）的动态控制下在I / O设备与主或扩展存储之间传输数据的系统
公开(公告)号：US5461721A
公开(公告)日：1995-10-24
申请号：US46679
申请日：1993-04-14
申请人： Roger L. Cormier , Robert J. Dugan , Kenneth J. Fredericks , Peter H. Gum , Moon J. Kim , Allen H. Preston , Richard J. Schmalz, deceased , Charles F. Webb , Leslie W. Wyman
发明人： Roger L. Cormier , Robert J. Dugan , Kenneth J. Fredericks , Peter H. Gum , Moon J. Kim , Allen H. Preston , Richard J. Schmalz, deceased , Charles F. Webb , Leslie W. Wyman
IPC分类号： G06F12/08 , G06F12/10 , G06F13/12
CPC分类号： G06F13/122 , G06F12/08 , G06F12/10
摘要： Enables an I/O channel program to use IDAWs (indirect data address words) to control data transfers from/to an I/O (input/output) device to/from either or both of ES (expanded storage) and/or system MS (main storage), in which data moved to/from ES does not move through MS. ES and MS are plural electronic storage media in a data processing system, and the I/O device is any I/O device selectable by the system. Intermixing of data transfers between ES and MS may be controlled by a single IDAW list accessed by a channel control word (CCW) in a channel program in a data transfer direction indicated in the CCW without any channel mode change.
摘要翻译：启用I / O通道程序以使用IDAW（间接数据地址字）来控制从I / O（输入/输出）设备到/从ES（扩展存储）和/或系统MS之一或两者的数据传输（主存储），其中移动到/从ES的数据不通过MS移动。 ES和MS是数据处理系统中的多个电子存储介质，I / O设备是可由系统选择的任何I / O设备。在ES和MS之间的数据传输的混合可以由在CCW中指示的数据传送方向上的信道程序中由信道控制字（CCW）访问的单个IDAW列表来控制，而没有任何信道模式改变。

3. 发明授权

US5423013A System for addressing a very large memory with real or virtual addresses using address mode registers 失效
标题翻译：使用地址模式寄存器寻址具有实际或虚拟地址的非常大的存储器的系统
公开(公告)号：US5423013A
公开(公告)日：1995-06-06
申请号：US754810
申请日：1991-09-04
申请人： Richard I. Baum , Brent A. Carlson , Moon J. Kim , Michael G. Mall , Casper A. Scalzi , Bhaskar Sinha
发明人： Richard I. Baum , Brent A. Carlson , Moon J. Kim , Michael G. Mall , Casper A. Scalzi , Bhaskar Sinha
IPC分类号： G06F9/32 , G06F9/355 , G06F12/02 , G06F12/06 , G06F12/10 , G06F12/08
CPC分类号： G06F9/342 , G06F12/0292 , G06F12/0623 , G06F9/32 , G06F2212/206
摘要： Allows instructions and data to be located in any one or more of plural sections of a large-size real memory of a data processing system. Any memory section is located by concatenating a conventional small real/absolute address with an address extender used with conventional small-size memory. A Central Processor Extended Address Mode (CPEAM) register content indicates the location of extenders in an AR(s), ASTE(s), STE(s) or PTE(s) for use by a central processor or I/O operations. An Input-Output Extended Address Mode (IOEAM) register content indicates the location of the extenders in ORB(s), CCW(s) or IDAW(s) for use by I/O operations. A compatible mode sets the content to zero for either or both of the CPEAM and IOEAM if either or both is not to be used.
摘要翻译：允许指令和数据位于数据处理系统的大尺寸实际存储器的多个部分中的任何一个或多个中。任何存储器部分通过将传统的小实际/绝对地址与传统的小尺寸存储器使用的地址扩展器连接来定位。中央处理器扩展地址模式（CPEAM）寄存器内容指示AR（s），ASTE，STE（s）或PTE的扩展器的位置，供中央处理器或I / O操作使用。输入输出扩展地址模式（IOEAM）寄存器内容指示扩展器在ORB（s），CCW（s）或IDAW中的位置，供I / O操作使用。如果不使用任何一个或两个，则兼容模式将CPEAM和IOEAM中的一个或两个设置为零。

4. 发明授权

US5371867A Method of using small addresses to access any guest zone in a large memory 失效
标题翻译：使用小地址访问大型内存中的任何访客区域的方法
公开(公告)号：US5371867A
公开(公告)日：1994-12-06
申请号：US974393
申请日：1992-11-10
申请人： Jonel George , Roger E. Hough , Moon J. Kim , Allen H. Preston , David E. Stucki , Charles F. Webb
发明人： Jonel George , Roger E. Hough , Moon J. Kim , Allen H. Preston , David E. Stucki , Charles F. Webb
IPC分类号： G06F12/06 , G06F9/46 , G06F12/02 , G06F12/10 , G06F12/08
CPC分类号： G06F12/10
摘要： Enables a host (hypervisor) to access any location in any guest zone in a large memory, when host and guest operands have small addresses that cannot access locations outside of their own zones. System hardware/microcode provides a particular number of windows for host use. Each CPU in the system has one or more window access registers (WARs), and one or more window registers (WRs). The host uses a load WAR instruction to designate each page frame (PF) in the host zone to be used as a host window, and each PF is associated with a respective window number. When the host receives an interception signal requiring the host to access a guest location represented by a guest zone identifier and a guest small address, the host designates one of its window numbers for an access to this guest location. Then, the host executes an activate WR instruction which invokes CPU hardware/microcode that generates a large absolute address for accessing this guest location in the large memory and stores it in a WR associated with the window number. When the host thereafter executes any instruction with an operand small address accessing the host window PF associated with that WR, and CPU hardware/microcode automatically substitutes that guest large address in the WR for the host operand small address for accessing the guest location.
摘要翻译：当主机和访客操作数具有不能访问其本身区域之外的位置的小地址时，使主机（管理程序）能够访问大内存中任何访客区域中的任何位置。系统硬件/微码提供特定数量的主机使用的窗口。系统中的每个CPU都有一个或多个窗口访问寄存器（WARs）和一个或多个窗口寄存器（WR）。主机使用加载WAR指令来指定要用作主机窗口的主机区域中的每个页面帧（PF），并且每个PF与相应的窗口编号相关联。当主机接收到要求主机访问由客户区域标识符和客人小地址表示的客户位置的拦截信号时，主机指定其窗口号码之一用于访问该访客位置。然后，主机执行一个激活WR指令，该指令调用生成大型绝对地址的CPU硬件/微码，用于访问大存储器中的该客户位置，并将其存储在与窗口号相关联的WR中。当主机此后执行任何具有访问与该WR相关联的主机窗口PF的操作数小地址的指令，并且CPU硬件/微代码自动地将该客户机大地址替换为用于访问客户位置的主操作数小地址。

5. 发明授权

US10223672B2 Method, system, and program product for differentially displaying an instant messaging (IM) availability 有权
公开(公告)号：US10223672B2
公开(公告)日：2019-03-05
申请号：US11612511
申请日：2006-12-19
申请人： Soobaek Jang , Moon J. Kim , Nianjun Zhou
发明人： Soobaek Jang , Moon J. Kim , Nianjun Zhou
IPC分类号： G06Q10/10 , H04L12/58 , G06F12/14
摘要： The invention provides a method, system, and program product for differentially displaying an instant messaging (IM) availability to a plurality of potential interlocutors. In one embodiment, the invention includes creating a relationship chart of potential interlocutors based on an organizational chart; defining a willingness to communicate, including a temporal component; establishing an IM availability for each potential interlocutor using the relationship chart and the willingness to communicate; sending the IM availability to a server; transmitting the IM availability from the server to a potential interlocutor's computing device capable of displaying the IM availability; receiving an IM invitation from an interlocutor; and generating an alert based on the IM availability for the interlocutor.

6. 发明授权

US09948813B2 Time-varying barcode in an active display 有权
公开(公告)号：US09948813B2
公开(公告)日：2018-04-17
申请号：US15174167
申请日：2016-06-06
申请人： Moon J. Kim
发明人： Moon J. Kim
IPC分类号： H04N1/047 , G06K7/10 , H04B10/116 , G06K7/14 , G06K19/06 , H04N1/028
CPC分类号： H04N1/047 , G06K7/10722 , G06K7/1095 , G06K7/1447 , G06K19/06028 , G06K19/06075 , G06K19/06112 , H04B10/116 , H04N1/028
摘要： Embodiments of the present invention provide barcode sequences in an active display for information exchange. Specifically, embodiments of the present invention provide a system and method for communicating information between electronic devices via a barcode image sequence. In a typical embodiment, a barcode image sequence is displayed on the display screen of a first electronic device. A second electronic device reads and decodes the barcode image sequence. The second electronic device displays an acknowledgement on the display screen of the second electronic device. The acknowledgement is read by the first electronic device.

7. 发明授权

US09886389B2 Cache memory bypass in a multi-core processor (MCP) 有权
公开(公告)号：US09886389B2
公开(公告)日：2018-02-06
申请号：US12276072
申请日：2008-11-21
申请人： Dan P. Dumarot , Karl J. Duvalsaint , Daeik Kim , Moon J. Kim , Eugene B. Risi
发明人： Dan P. Dumarot , Karl J. Duvalsaint , Daeik Kim , Moon J. Kim , Eugene B. Risi
IPC分类号： G06F12/08 , G06F12/0888 , G06F11/16 , G06F12/0811 , G06F11/20 , G06F12/0813 , G06F12/084
CPC分类号： G06F12/0888 , G06F11/1666 , G06F11/2035 , G06F11/2043 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F2212/1032
摘要： This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

8. 发明授权

US09613357B2 Authorizing the use of a biometric card 有权
公开(公告)号：US09613357B2
公开(公告)日：2017-04-04
申请号：US14747131
申请日：2015-06-23
申请人： Moon J. Kim
发明人： Moon J. Kim
IPC分类号： G06K5/00 , G06Q20/40 , G06K19/077 , G06Q20/10 , G06K9/00 , H01S5/34 , H01S5/183 , H01S5/187
CPC分类号： G06Q20/40145 , G06K9/00013 , G06K9/0012 , G06K19/0718 , G06K19/07701 , G06Q20/105 , G06Q20/341 , G06Q20/409 , H01S5/0264 , H01S5/183 , H01S5/187 , H01S5/34 , H01S5/423
摘要： Embodiments of the present invention provide a system and method for authorizing the use of a biometric transaction card. Specifically, embodiments of the present invention provide a biometric card having a biometric sensor to determine whether the biometric information (fingerprint) is from human skin. In a typical embodiment, the cardholder approaches a magnetic reader with the card. The user places his/her finger on the SpO2 sensor of the card. The sensor estimates the SpO2 level. Card authorization is based, in part, on the estimated SpO2 level.

9. 发明申请

US20160049386A1 SELF-ORGANIZING NETWORK WITH CHIP PACKAGE HAVING MULTIPLE INTERCONNECTION CONFIGURATIONS 审中-公开
标题翻译：自组织网络与具有多个互连配置的芯片包
公开(公告)号：US20160049386A1
公开(公告)日：2016-02-18
申请号：US14925115
申请日：2015-10-28
申请人： Moon J. Kim
发明人： Moon J. Kim
IPC分类号： H01L25/065 , G06F13/40 , H01L25/00 , H01L23/00 , H01L23/48
CPC分类号： H01L25/0657 , G06F13/4022 , G06F13/4068 , H01L23/481 , H01L23/525 , H01L23/5283 , H01L24/06 , H01L24/14 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/50 , H01L2224/02371 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/06188 , H01L2224/13025 , H01L2224/14181 , H01L2224/14183 , H01L2224/16137 , H01L2224/16146 , H01L2224/16157 , H01L2224/81191 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06551 , H01L2225/06565 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2224/05552
摘要： In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc. Among other things, the use of backend side interconnects allows maximum surface area of the chip package to be utilized and provides increased reliability. These advantages are especially realized when used in conjunction with vertical TSVs.
摘要翻译：通常，本发明的实施例提供具有多个TSV配置的芯片封装。具体地，芯片封装通常包括后端层（例如，金属互连层）; 耦合到所述后端层的衬底; 从后端层的侧表面延伸（例如角度地）到后端层的底表面的一组（至少一个）后端侧互连; 一组可选的垂直TSV，从后端层的顶表面延伸穿过衬底; 以及位于基板组织器中的网络组织器，用于处理使用该组后端侧互连和一组垂直TSV形成的通信。可以将一组连接（例如，可控制的崩溃芯片连接（C4））定位成与任何通孔相邻，以连接到其他硬件元件，例如附加的芯片封装，总线等。其中，使用后端侧互连允许使用芯片封装的最大表面积并提供增加的可靠性。当与垂直TSV结合使用时，这些优点特别实现。

10. 发明授权

US09189675B2 Adaptive fingerprint scanning 有权
标题翻译：自适应指纹扫描
公开(公告)号：US09189675B2
公开(公告)日：2015-11-17
申请号：US13096179
申请日：2011-04-28
申请人： Moon J. Kim
发明人： Moon J. Kim
IPC分类号： G06K9/00
CPC分类号： G06K9/0002
摘要： Embodiments of the present invention provide an adaptive and intelligent fingerprint scanning device and approach. Specifically, embodiments of the present invention utilize DC resistive image scanning to reduce overall scanning time and energy consumption (e.g., by identifying a targeted scanning area). In a typical embodiment, a scanning device will be provided that includes a scanning area comprised of a set (e.g., at least one) of imaging pixel electrodes (e.g., arranged adjacent to one another in a grid-like or other fashion). As a user presses his/her finger against the scanning area, a first portion of the finger will contact a first electrode while a second portion of the finger will contact a second electrode. When this occurs, a voltage source of the device will apply an initial voltage across the first and second finger portions. A meter of the device will take an electrical measurement (e.g., resistance and/or charged skin voltage) across the two finger portions. Based on the electrical measurement, a location of the finger on the device will be identified, and the fingerprint will be scanned accordingly. Thus, the entire scanning surface need not be scanned, only the portions thereof where the finger was detected.
摘要翻译：本发明的实施例提供了一种自适应和智能的指纹扫描装置和方法。具体地，本发明的实施例利用DC电阻图像扫描来减少总扫描时间和能量消耗（例如，通过识别目标扫描区域）。在典型的实施例中，将提供一种扫描装置，其包括由成像像素电极（例如，以格子状或其他方式彼此相邻布置）的组（例如至少一个）组成的扫描区域。当用户将他/她的手指压靠扫描区域时，手指的第一部分将接触第一电极，而手指的第二部分将接触第二电极。当这种情况发生时，装置的电压源将施加跨越第一和第二手指部分的初始电压。设备的一米将跨两个手指部分进行电测量（例如，电阻和/或带电皮肤电压）。基于电测量，将识别手指在设备上的位置，并且相应地扫描指纹。因此，整个扫描表面不需要被扫描，仅仅是其中检测到手指的部分。

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