专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5371867A Method of using small addresses to access any guest zone in a large memory 失效
标题翻译：使用小地址访问大型内存中的任何访客区域的方法
公开(公告)号：US5371867A
公开(公告)日：1994-12-06
申请号：US974393
申请日：1992-11-10
申请人： Jonel George , Roger E. Hough , Moon J. Kim , Allen H. Preston , David E. Stucki , Charles F. Webb
发明人： Jonel George , Roger E. Hough , Moon J. Kim , Allen H. Preston , David E. Stucki , Charles F. Webb
IPC分类号： G06F12/06 , G06F9/46 , G06F12/02 , G06F12/10 , G06F12/08
CPC分类号： G06F12/10
摘要： Enables a host (hypervisor) to access any location in any guest zone in a large memory, when host and guest operands have small addresses that cannot access locations outside of their own zones. System hardware/microcode provides a particular number of windows for host use. Each CPU in the system has one or more window access registers (WARs), and one or more window registers (WRs). The host uses a load WAR instruction to designate each page frame (PF) in the host zone to be used as a host window, and each PF is associated with a respective window number. When the host receives an interception signal requiring the host to access a guest location represented by a guest zone identifier and a guest small address, the host designates one of its window numbers for an access to this guest location. Then, the host executes an activate WR instruction which invokes CPU hardware/microcode that generates a large absolute address for accessing this guest location in the large memory and stores it in a WR associated with the window number. When the host thereafter executes any instruction with an operand small address accessing the host window PF associated with that WR, and CPU hardware/microcode automatically substitutes that guest large address in the WR for the host operand small address for accessing the guest location.
摘要翻译：当主机和访客操作数具有不能访问其本身区域之外的位置的小地址时，使主机（管理程序）能够访问大内存中任何访客区域中的任何位置。系统硬件/微码提供特定数量的主机使用的窗口。系统中的每个CPU都有一个或多个窗口访问寄存器（WARs）和一个或多个窗口寄存器（WR）。主机使用加载WAR指令来指定要用作主机窗口的主机区域中的每个页面帧（PF），并且每个PF与相应的窗口编号相关联。当主机接收到要求主机访问由客户区域标识符和客人小地址表示的客户位置的拦截信号时，主机指定其窗口号码之一用于访问该访客位置。然后，主机执行一个激活WR指令，该指令调用生成大型绝对地址的CPU硬件/微码，用于访问大存储器中的该客户位置，并将其存储在与窗口号相关联的WR中。当主机此后执行任何具有访问与该WR相关联的主机窗口PF的操作数小地址的指令，并且CPU硬件/微代码自动地将该客户机大地址替换为用于访问客户位置的主操作数小地址。

2. 发明授权

US5461721A System for transferring data between I/O devices and main or expanded storage under dynamic control of independent indirect address words (IDAWs) 失效
标题翻译：用于在独立间接地址字（IDAW）的动态控制下在I / O设备与主或扩展存储之间传输数据的系统
公开(公告)号：US5461721A
公开(公告)日：1995-10-24
申请号：US46679
申请日：1993-04-14
申请人： Roger L. Cormier , Robert J. Dugan , Kenneth J. Fredericks , Peter H. Gum , Moon J. Kim , Allen H. Preston , Richard J. Schmalz, deceased , Charles F. Webb , Leslie W. Wyman
发明人： Roger L. Cormier , Robert J. Dugan , Kenneth J. Fredericks , Peter H. Gum , Moon J. Kim , Allen H. Preston , Richard J. Schmalz, deceased , Charles F. Webb , Leslie W. Wyman
IPC分类号： G06F12/08 , G06F12/10 , G06F13/12
CPC分类号： G06F13/122 , G06F12/08 , G06F12/10
摘要： Enables an I/O channel program to use IDAWs (indirect data address words) to control data transfers from/to an I/O (input/output) device to/from either or both of ES (expanded storage) and/or system MS (main storage), in which data moved to/from ES does not move through MS. ES and MS are plural electronic storage media in a data processing system, and the I/O device is any I/O device selectable by the system. Intermixing of data transfers between ES and MS may be controlled by a single IDAW list accessed by a channel control word (CCW) in a channel program in a data transfer direction indicated in the CCW without any channel mode change.
摘要翻译：启用I / O通道程序以使用IDAW（间接数据地址字）来控制从I / O（输入/输出）设备到/从ES（扩展存储）和/或系统MS之一或两者的数据传输（主存储），其中移动到/从ES的数据不通过MS移动。 ES和MS是数据处理系统中的多个电子存储介质，I / O设备是可由系统选择的任何I / O设备。在ES和MS之间的数据传输的混合可以由在CCW中指示的数据传送方向上的信道程序中由信道控制字（CCW）访问的单个IDAW列表来控制，而没有任何信道模式改变。

3. 发明授权

US10338923B2 Branch prediction path wrong guess instruction 有权
公开(公告)号：US10338923B2
公开(公告)日：2019-07-02
申请号：US12435631
申请日：2009-05-05
申请人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
发明人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
IPC分类号： G06F9/30 , G06F9/38 , G06F12/0862 , G06F8/41
摘要： A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.

4. 发明授权

US08621180B2 Dynamic address translation with translation table entry format control for identifying format of the translation table entry 有权
标题翻译：动态地址转换与翻译表格格式控制，用于识别翻译表格的格式
公开(公告)号：US08621180B2
公开(公告)日：2013-12-31
申请号：US13336106
申请日：2011-12-23
申请人： Dan F Greiner , Lisa C Heller , Damian L Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： Dan F Greiner , Lisa C Heller , Damian L Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1009 , G06F12/1027
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.
摘要翻译：提供的是增强的动态地址转换设施。在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。虚拟地址的索引部分用于引用转换表中的条目。如果启用了转换表条目中包含的格式控制字段，则表项包含大小至少为1M字节的大块数据的帧地址。然后将帧地址与虚拟地址的偏移部分组合以形成主存储器或存储器中的小4K字节数据块的转换地址。

5. 发明授权

US08112174B2 Processor, method and computer program product for fast selective invalidation of translation lookaside buffer 有权
标题翻译：处理器，方法和计算机程序产品，用于快速选择性地无效翻译后备缓冲区
公开(公告)号：US08112174B2
公开(公告)日：2012-02-07
申请号：US12036398
申请日：2008-02-25
申请人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
发明人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided.
摘要翻译：一种处理器，包括适于使至少一个逻辑地址映射至少一个绝对地址无效的微体系结构，包括：至少一个翻译后备缓冲器（TLB）及其多个副本; 独立索引TLB每份副本的逻辑; 多个比较器，每个比较器与每个TLB端口的每个TLB组输出的相应输出相关联，其中每个比较器适于识别无效化的映射; 以及使每个识别的映射无效的逻辑。提供了一种方法和计算机程序产品。

6. 发明申请

US20110320774A1 OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE 有权
标题翻译：操作控制作为分支机构的功能
公开(公告)号：US20110320774A1
公开(公告)日：2011-12-29
申请号：US12822379
申请日：2010-06-24
申请人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
发明人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3806 , G06F9/3844 , G06F9/3857
摘要： A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.
摘要翻译：一种用于数据操作数取出控制的系统包括一计算机处理器，该计算机处理器包括用于确定存储器访问操作的控制控制单元被配置为执行方法。该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。该方法还包括将尝试访问系统存储器的所选择的指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

7. 发明授权

US07966474B2 System, method and computer program product for translating storage elements 有权
标题翻译：用于翻译存储元件的系统，方法和计算机程序产品
公开(公告)号：US07966474B2
公开(公告)日：2011-06-21
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/26
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

8. 发明申请

US20100287358A1 Branch Prediction Path Instruction 审中-公开
标题翻译：分支预测路径指令
公开(公告)号：US20100287358A1
公开(公告)日：2010-11-11
申请号：US12435631
申请日：2009-05-05
申请人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
发明人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30047 , G06F8/4442 , G06F9/3005 , G06F9/30054 , G06F9/30058 , G06F9/30076 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/383 , G06F9/3842 , G06F9/3844 , G06F9/3846 , G06F9/3848 , G06F12/0862 , G06F2212/6028
摘要： A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.
摘要翻译：一种分支预测方法，所述方法包括：接收具有分支错误猜测指令地址的分支错误猜测指令和包括操作码和分支目标地址的数据，确定分支错误猜测指令是否由分支预测机制预测，发送分支对执行单元的错误猜测指令响应于确定分支错误猜测指令由分支预测机制预测，以及在分支目标地址处的接收和解码指令。

9. 发明申请

US20090217264A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING FILTERING OF GUEST2 QUIESCE REQUESTS 失效
标题翻译：方法，系统和计算机程序产品，用于提供GUEST2 QUIESCE要求的过滤
公开(公告)号：US20090217264A1
公开(公告)日：2009-08-27
申请号：US12037887
申请日：2008-02-26
申请人： Lisa C. Heller , Damian L. Osisek , Charles F. Webb
发明人： Lisa C. Heller , Damian L. Osisek , Charles F. Webb
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45566
摘要： A method, system and computer program product for providing filtering of level two guest (G2) quiesce requests. The method includes receiving a G2 quiesce interruption request at a processor currently or previously executing a G2 running under a level two hypervisor in a logical partition. The G2 includes a current zone and G2 virtual machine (VM) identifier. The quiesce interruption request specifies an initiating zone and an initiating G2 VM identifier. It is determined if the G2 quiesce interruption request can be filtered by the processor. The determining is responsive to the current G2 VM identifier, the current zone, the initiating zone and the initiating G2 VM identifier. The G2 quiesce interruption request is filtered at the processor in response to determining that the G2 quiesce interruption request can be filtered. Thus, filtering between G2 virtual machines running in the logical partition is provided.
摘要翻译：一种用于提供二级客户（G2）静默请求过滤的方法，系统和计算机程序产品。该方法包括在当前或先前执行在逻辑分区中的二级虚拟机管理程序下运行的G2的处理器处接收G2停顿中断请求。 G2包括当前区域和G2虚拟机（VM）标识符。静默中断请求指定启动区域和启动G2 VM标识符。确定G2停顿中断请求是否可以被处理器过滤。该确定响应于当前的G2 VM标识符，当前区域，起始区域和起始G2 VM标识符。响应于确定可以过滤G2静默中断请求，在处理器处对G2静默中断请求进行过滤。因此，提供了在逻辑分区中运行的G2虚拟机之间的过滤。

10. 发明授权

US06671793B1 Method and system for managing the result from a translator co-processor in a pipelined processor 有权
标题翻译：用于管理流水线处理器中的翻译协处理器的结果的方法和系统
公开(公告)号：US06671793B1
公开(公告)日：2003-12-30
申请号：US09678061
申请日：2000-10-02
申请人： Scott B. Swaney , Mark S. Farrell , John D. MacDougall , Hans-Juergen Muenster , Charles F. Webb
发明人： Scott B. Swaney , Mark S. Farrell , John D. MacDougall , Hans-Juergen Muenster , Charles F. Webb
IPC分类号： G06F1516
CPC分类号： G06F9/3017 , G06F9/3842 , G06F9/3861 , G06F9/3863 , G06F9/3879
摘要： An exemplary embodiment of the invention is a method and system for managing a result returned from a translator co-processor to a recovery unit of a central processor. The computer system has a pipelined computer processor and a pipelined central processor, which executes an instruction set in a hardware controlled execution unit and executes an instruction set in a milli-mode architected state with a millicode sequence of instructions in the hardware controlled execution unit. The central processor initiates a request to the translator co-processor a cycle after decode of a perform translator operation instruction in the millicode sequence. The translator co-processor processes the perform translator operation instruction to generate a perform translator operation result. The translator co-processor returns the results to a recovery unit of the central processor. The recovery unit stores the perform translator operation result in a system register. The request for the perform translator operation result by the central processor is interlocked by a hardware interlock of the recovery unit until the translator co-processor returns the perform translator operation result. The mechanism allows the recovery unit to maintain the correct perform translator operation result with speculative execution and instruction level retry recovery throughout the duration of the perform translator operation.
摘要翻译：本发明的示例性实施例是用于管理从翻译器协处理器返回到中央处理器的恢复单元的结果的方法和系统。计算机系统具有流水线计算机处理器和流水线中央处理器，其执行硬件控制执行单元中的指令集，并且在硬模式执行单元中以毫列指令序列执行毫模式架构状态指令集。中央处理器在解码执行转换器操作指令之后的一个循环中向转译器协处理器发出一个请求。翻译协处理器处理执行翻译器操作指令以产生执行转换器操作结果。翻译协处理器将结果返回到中央处理器的恢复单元。恢复单元将执行转换器操作结果存储在系统寄存器中。由中央处理器执行的执行转换器操作结果的请求由恢复单元的硬件互锁互锁，直到转换器协处理器返回执行转换器操作结果。该机制允许恢复单元在执行转换器操作的整个持续时间内通过推测执行和指令级重试恢复来维持正确的执行转换器操作结果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式