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1. 发明授权

US09886389B2 Cache memory bypass in a multi-core processor (MCP) 有权
公开(公告)号：US09886389B2
公开(公告)日：2018-02-06
申请号：US12276072
申请日：2008-11-21
申请人： Dan P. Dumarot , Karl J. Duvalsaint , Daeik Kim , Moon J. Kim , Eugene B. Risi
发明人： Dan P. Dumarot , Karl J. Duvalsaint , Daeik Kim , Moon J. Kim , Eugene B. Risi
IPC分类号： G06F12/08 , G06F12/0888 , G06F11/16 , G06F12/0811 , G06F11/20 , G06F12/0813 , G06F12/084
CPC分类号： G06F12/0888 , G06F11/1666 , G06F11/2035 , G06F11/2043 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F2212/1032
摘要： This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

2. 发明申请

US20100131717A1 CACHE MEMORY BYPASS IN A MULTI-CORE PROCESSOR (MCP) 有权
标题翻译：多核处理器（MCP）中的高速缓存存储器旁路
公开(公告)号：US20100131717A1
公开(公告)日：2010-05-27
申请号：US12276072
申请日：2008-11-21
申请人： Dan P. Dumarot , Karl J. Duvalsaint , Daeik Kim , Moon J. Kim , Eugene B. Risi
发明人： Dan P. Dumarot , Karl J. Duvalsaint , Daeik Kim , Moon J. Kim , Eugene B. Risi
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F11/1666 , G06F11/2035 , G06F11/2043 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F2212/1032
摘要： This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.
摘要翻译：本发明描述了一种用于多核处理器的装置，计算机体系结构，存储器结构，存储器控制和高速缓存存储器操作方法。逻辑内核以低产出或致命性能绕过即时缓存单元。核心安装（多个）高速缓存单元可能已被其他逻辑内核使用。所选高速缓存存储单元提供具有相同内容的多个逻辑核。共享高速缓冲存储器单元为所有安装核心提供缓存搜索，命中，未命中和回写功能。该方法通过共享可能已经接合其他逻辑核心的高速缓存存储器块来恢复其高速缓冲存储器块不可操作的逻辑核心。该方法用于提高剩余系统的可靠性和性能。

3. 发明申请

US20130124840A1 SECURE BOOT UP OF A COMPUTER BASED ON A HARDWARE BASED ROOT OF TRUST 失效
标题翻译：基于硬件的信任基础的计算机的安全启动
公开(公告)号：US20130124840A1
公开(公告)日：2013-05-16
申请号：US13294467
申请日：2011-11-11
申请人： Vincent V. Diluoffo , Dan P. Dumarot , Eugene B. Risi
发明人： Vincent V. Diluoffo , Dan P. Dumarot , Eugene B. Risi
IPC分类号： G06F21/00 , G06F9/00
CPC分类号： G06F21/575 , G06F9/4401
摘要： A method includes performing a boot up of a computer having a system on-chip having multiple processors and a nonvolatile read-only machine-readable medium. The boot up includes enabling a first processor of the multiple processors, while maintaining others of the multiple processors in a disabled state. The boot up includes retrieving initial stage instructions from the nonvolatile read-only machine-readable medium. The boot up also includes executing the initial stage instructions and validating multiple stages of firmware separately. The boot up includes, in response to validating the multiple stages of firmware, executing the multiple stages of firmware in consecutive stages of the boot up, wherein executing of each stage of the multiple stages of firmware enables a different set of disabled hardware components of the computer. The boot up also includes validating an operating system and, in response to validation, transferring control of the computer to the operating system.
摘要翻译：一种方法包括执行具有片上系统的具有多个处理器的计算机和非易失性只读机器可读介质的引导。启动包括启用多个处理器的第一处理器，同时将多个处理器中的其他处理器保持在禁用状态。启动包括从非易失性只读机器可读介质检索初始级指令。启动还包括执行初始阶段指令并分别验证多个阶段的固件。启动包括响应于验证固件的多个阶段，在引导的连续阶段中执行固件的多个阶段，其中执行多级固件的每个阶段使得不同的一组固定的硬件组件电脑。引导还包括验证操作系统，并且响应于验证，将计算机的控制转移到操作系统。

4. 发明授权

US08775784B2 Secure boot up of a computer based on a hardware based root of trust 失效
标题翻译：基于基于硬件的信任根安全地启动计算机
公开(公告)号：US08775784B2
公开(公告)日：2014-07-08
申请号：US13294467
申请日：2011-11-11
申请人： Vincent V. Diluoffo , Dan P. Dumarot , Eugene B. Risi
发明人： Vincent V. Diluoffo , Dan P. Dumarot , Eugene B. Risi
IPC分类号： G06F7/04 , G06F9/00 , G06F12/14 , G06F15/177
CPC分类号： G06F21/575 , G06F9/4401
摘要： A method includes performing a boot up of a computer having a system on-chip having multiple processors and a nonvolatile read-only machine-readable medium. The boot up includes enabling a first processor of the multiple processors, while maintaining others of the multiple processors in a disabled state. The boot up includes retrieving initial stage instructions from the nonvolatile read-only machine-readable medium. The boot up also includes executing the initial stage instructions and validating multiple stages of firmware separately. The boot up includes, in response to validating the multiple stages of firmware, executing the multiple stages of firmware in consecutive stages of the boot up, wherein executing of each stage of the multiple stages of firmware enables a different set of disabled hardware components of the computer. The boot up also includes validating an operating system and, in response to validation, transferring control of the computer to the operating system.
摘要翻译：一种方法包括执行具有片上系统的具有多个处理器的计算机和非易失性只读机器可读介质的引导。启动包括启用多个处理器的第一处理器，同时将多个处理器中的其他处理器保持在禁用状态。启动包括从非易失性只读机器可读介质检索初始级指令。启动还包括执行初始阶段指令并分别验证多个阶段的固件。启动包括响应于验证固件的多个阶段，在引导的连续阶段中执行固件的多个阶段，其中执行多级固件的每个阶段使得不同的一组固定的硬件组件电脑。引导还包括验证操作系统，并且响应于验证，将计算机的控制转移到操作系统。

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