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1. 发明授权

US4986666A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4986666A
公开(公告)日：1991-01-22
申请号：US277261
申请日：1988-11-29
申请人： Noriyuki Homma , Hisayuki Higuchi , Yoji Idei , Hiroaki Nambu , Yoshiaki Sakurai
发明人： Noriyuki Homma , Hisayuki Higuchi , Yoji Idei , Hiroaki Nambu , Yoshiaki Sakurai
IPC分类号： G11C7/06 , G11C7/10 , G11C8/10 , G11C11/416
CPC分类号： G11C7/1057 , G11C11/416 , G11C7/062 , G11C7/065 , G11C7/1039 , G11C7/1051 , G11C8/10
摘要： A semiconductor memory device capable of operating at high speeds, and a sense circuit and a decoder circuit that can be suitably used for the memory device. A latch function is imparted to at least either one of the decoder circuit or the sense circuit in the semiconductor memory device.
摘要翻译：能够高速运行的半导体存储器件，以及适用于存储器件的读出电路和解码器电路。锁存功能被赋予半导体存储器件中的解码器电路或感测电路中的至少一个。

2. 发明授权

US5398201A Bit-line drive circuit for a semiconductor memory 失效
标题翻译：半导体存储器的位线驱动电路
公开(公告)号：US5398201A
公开(公告)日：1995-03-14
申请号：US53330
申请日：1993-04-28
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Hisayuki Higuchi , Kazuo Kanetani , Youji Idei , Ken'ichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Hisayuki Higuchi , Kazuo Kanetani , Youji Idei , Ken'ichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa
IPC分类号： G11C5/14 , G11C7/10 , G11C11/34
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished. The improvement of the drivers of word lines and bit lines is also disclosed and a semiconductor memory which can operate at a high speed as a whole semiconductor memory can be realized.
摘要翻译：一种适于实现存储器的高速的电路技术，其以使得存储器单元包括场效应晶体管和外围电路的方式构造，包括双极晶体管和场效应晶体管。根据本发明，将集电极连接到差分放大器并根据输入到基极或发射极的信号向差分放大器提供电流的双极晶体管和双极晶体管，以提供电流只有写入位线才能连接。根据本发明，通过切换选择位线来读取信息时的访问时间的高速度被实现。此外，当写入信息时位线的充电/放电时间减少，并且也可以实现高速的写入时间。还公开了字线和位线的驱动器的改进，并且可以实现可以作为整个半导体存储器以高速度操作的半导体存储器。

3. 发明授权

US5163022A Semiconductor cell memory with current sensing 失效
标题翻译：具有电流检测功能的半导体单元存储器
公开(公告)号：US5163022A
公开(公告)日：1992-11-10
申请号：US827873
申请日：1992-01-30
申请人： Noriyuki Homma , Hiroaki Nambu , Kunihiko Yamaguchi , Tohru Nakamura , Youji Idei , Kazuo Kanetani , Kenichi Ohhata , Yoshiaki Sakurai , Hisayuki Higuchi
发明人： Noriyuki Homma , Hiroaki Nambu , Kunihiko Yamaguchi , Tohru Nakamura , Youji Idei , Kazuo Kanetani , Kenichi Ohhata , Yoshiaki Sakurai , Hisayuki Higuchi
IPC分类号： G11C7/06 , G11C11/411 , G11C11/412 , G11C11/416 , G11C11/419
CPC分类号： G11C11/4113 , G11C11/412 , G11C11/416 , G11C11/419 , G11C7/062
摘要： The disclosure includes feeding a current I.sub.R to only BIT lines selected, or feeding current I.sub.R transiently to only the BIT lines switched from unselected to selected states; and a sense amplifier for detecting the difference between the currents flowing in selected BIT lines to read out stored information, wherein current I.sub.R and cell current I.sub.cell have a relation of I.sub.R >I.sub.cell. The BiC MOS memory has high speed, low power and high integration density. Diodes are provided between the memory cell and the BIT lines.
摘要翻译：本公开包括将电流IR馈送到仅选择的BIT线，或者将电流IR瞬时馈送到仅从未选择状态切换到选定状态的BIT线; 以及读出放大器，用于检测在所选择的BIT行中流动的电流之间的差以读出存储的信息，其中当前的IR和单元电流Icell具有IR> Icell的关系。 BiC MOS存储器具有高速度，低功耗和高集成度。在存储单元和BIT线之间提供二极管。

4. 发明授权

US5255225A Semiconductor integrated circuit device and memory consisting of semiconductor integrated circuit 失效
标题翻译：半导体集成电路器件和存储器由半导体集成电路组成
公开(公告)号：US5255225A
公开(公告)日：1993-10-19
申请号：US845557
申请日：1992-03-04
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
IPC分类号： G11C5/14 , G11C7/10 , G11C11/40
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided.A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor.The speed of an operation of the circuit device can be increased to a high level owing to a simple circuit in which a level, which is required to attain an output amplitude, of complementary output signals is secured by the current switch circuit, the amplified complementary signals being inputted into the emitter follower circuit to directly drive the output transistor.
摘要翻译：提供一种包括电平转换电路的半导体集成电路器件，其中电路的简化和操作速度的提高已经达到。通过包括接收输入信号和参考电压的差分晶体管的电流开关电路将被放大到所需信号电平的一对互补输出信号输入到一对发射极跟随器电路中。射极跟随器输出晶体管由来自一个射极跟随器电路的输出信号驱动，而在输出晶体管和用作负载的电流源之间提供的N沟道MOSFET由另一个射极跟随器电路的输出信号驱动到从输出晶体管的发射极获得电平放大的输出信号。电路装置的运行速度可以通过电流开关电路确保互补输出信号的达到输出幅度所需的电平的简单电路而增加到高电平，放大的互补信号被输入射极跟随器电路以直接驱动输出晶体管。

5. 发明授权

US5086414A Semiconductor device having latch means 失效
标题翻译：具有锁存装置的半导体装置
公开(公告)号：US5086414A
公开(公告)日：1992-02-04
申请号：US436770
申请日：1989-11-15
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Yoshiaki Sakurai , Jun Etoh
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Yoshiaki Sakurai , Jun Etoh
IPC分类号： G11C7/22 , G11C8/18 , H03K3/2885 , H03K3/356
CPC分类号： G11C7/22 , G11C8/18 , H03K3/2885 , H03K3/356113 , H03K3/356156
摘要： A semiconductor circuit having a plurality of circuit blocks, each having latch circuits each one thereof being controlled by an internally provided clock signal for preventing malfunction of the circuit. Each circuit is provided with the latch function so that the cycle time is made shorter than the access time. Moreover, the latch means are driven in such a manner that the adjoining ones are prevented from being put to through-state simultaneously, whereby malfunction is prevented.
摘要翻译：具有多个电路块的半导体电路，每个具有锁存电路，每个电路块由内部提供的时钟信号控制，用于防止电路的故障。每个电路都具有锁存功能，使得周期时间短于访问时间。此外，锁定装置被驱动，使得相邻的锁定装置被阻止同时被置于通过状态，从而防止了故障。

6. 发明授权

US4642486A Decoder circuit using transistors or diodes of different characteristics 失效
标题翻译：解码电路采用晶体管或二极管的不同特性
公开(公告)号：US4642486A
公开(公告)日：1987-02-10
申请号：US686660
申请日：1984-12-27
申请人： Noriyuki Honma , Hiroaki Nambu , Isao Yoshida , Hisayuki Higuchi , Kunihiko Yamaguchi
发明人： Noriyuki Honma , Hiroaki Nambu , Isao Yoshida , Hisayuki Higuchi , Kunihiko Yamaguchi
IPC分类号： G11C11/413 , G11C11/34 , H03K17/60 , H03K17/62 , H03K19/013 , G11C8/00 , H03K19/082 , H03K19/092
CPC分类号： H03K17/603 , H03K17/6214
摘要： This invention is effective in the speeding up of a decoder circuit and maintenance of output amplitude. The invention is characterized in that, in a decoder circuit composed of a multi-emitter transistor or at least one diode group in which the anodes of a plurality of diodes are connected, and a charge circuit having an output emitter follower transistor, the multi-emitter transistor or the forward voltage of the diodes are larger than the voltage between the base and the emitter of the output emitter follower transistor.
摘要翻译：本发明在解码器电路的加速和输出振幅的维持方面是有效的。本发明的特征在于，在由多个发射极晶体管组成的解码器电路或连接有多个二极管的阳极的至少一个二极管组以及具有输出射极跟随器晶体管的充电电路的情况下，发射极晶体管或二极管的正向电压大于输出射极跟随器晶体管的基极和发射极之间的电压。

7. 发明授权

US07123534B2 Semiconductor memory device having short refresh time 失效
标题翻译：具有短刷新时间的半导体存储器件
公开(公告)号：US07123534B2
公开(公告)日：2006-10-17
申请号：US10943895
申请日：2004-09-20
申请人： Hiroaki Nambu , Noriyuki Homma
发明人： Hiroaki Nambu , Noriyuki Homma
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/4085 , G11C11/4096 , G11C2211/4065
摘要： A semiconductor memory device in which memory cells are arranged at intersections between the word lines and the bit lines includes a control unit for selecting, in a second half of a cycle in which a first word line is selected from the word lines to conduct a read or write operation for a first memory cell coupled with the first word line, a second word line other than the first word line and refreshing memory cells corresponding to the second word line. The memory cell includes an amplifier section including two driver transistors of which gate and drain electrodes are respectively cross-coupled with each other and a switch section including selector transistors coupling the amplifier section with the bit lines according to a selection signal on the bit line. Either one of each transistor and each selector transistor is an n-channel transistor or a p-type transistor.
摘要翻译：一种半导体存储器件，其中存储器单元布置在字线和位线之间的交叉处，包括控制单元，用于在从字线中选择第一字线以进行读取的周期的后半段中进行选择或与第一字线耦合的第一存储单元的写入操作，除第一字线以外的第二字线和对应于第二字线的刷新存储单元。存储单元包括放大器部分，其包括两个驱动晶体管，栅极和漏极彼此分别交叉耦合;以及开关部分，包括根据位线上的选择信号将放大器部分与位线耦合的选择晶体管。每个晶体管和每个选择晶体管中的任一个是n沟道晶体管或p型晶体管。

8. 发明授权

US5448527A Decoder and driver for use in a semiconductor memory 失效
标题翻译：用于半导体存储器的解码器和驱动器
公开(公告)号：US5448527A
公开(公告)日：1995-09-05
申请号：US149936
申请日：1993-11-10
申请人： Hiroaki Nambu , Noriyuki Homma , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Takesi Kusunoki
发明人： Hiroaki Nambu , Noriyuki Homma , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Takesi Kusunoki
IPC分类号： G11C11/413 , G11C8/08 , G11C8/10 , G11C8/00
CPC分类号： G11C8/10 , G11C8/08
摘要： A decoder formed of multiple circuit blocks each including bipolar transistors Q1 and Q2 having their collectors connected to resistors R1 and R2, respectively, a bipolar transistor Q3 having its collector supplied with a power voltage, and a current source I1 connected commonly to the emitters of Q1-Q3. This circuit configuration permits the decoder and BiCMOS memories using it to operate with a low supply voltage.
摘要翻译：由多个电路块形成的解码器，每个电路块分别包括双极晶体管Q1和Q2，它们的集电极分别连接到电阻器R1和R2，其集电极被提供有电源电压的双极晶体管Q3和共同连接到发射极的发射极 Q1-Q3。该电路配置允许使用它的解码器和BiCMOS存储器以低电源电压工作。

9. 发明申请

US20050063238A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050063238A1
公开(公告)日：2005-03-24
申请号：US10943895
申请日：2004-09-20
申请人： Hiroaki Nambu , Noriyuki Homma
发明人： Hiroaki Nambu , Noriyuki Homma
IPC分类号： H01L27/11 , G11C7/00 , G11C11/403 , G11C11/406 , G11C11/408 , G11C11/4096 , H01L21/8244
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/4085 , G11C11/4096 , G11C2211/4065
摘要： A semiconductor memory device in which memory cells are arranged at intersections between the word lines and the bit lines includes a control unit for selecting, in a second half of a cycle in which a first word line is selected from the word lines to conduct a read or write operation for a first memory cell coupled with the first word line, a second word line other than the first word line and refreshing memory cells corresponding to the second word line. The memory cell includes an amplifier section including two driver transistors of which gate and drain electrodes are respectively cross-coupled with each other and a switch section including selector transistors coupling the amplifier section with the bit lines according to a selection signal on the bit line. Either one of each transistor and each selector transistor is an n-channel transistor or a p-type transistor.
摘要翻译：一种半导体存储器件，其中存储器单元布置在字线和位线之间的交叉处，包括控制单元，用于在从字线中选择第一字线以进行读取的周期的后半段中进行选择或与第一字线耦合的第一存储单元的写入操作，除第一字线以外的第二字线和对应于第二字线的刷新存储单元。存储单元包括放大器部分，其包括两个驱动晶体管，栅极和漏极彼此分别交叉耦合;以及开关部分，包括根据位线上的选择信号将放大器部分与位线耦合的选择晶体管。每个晶体管和每个选择晶体管中的任一个是n沟道晶体管或p型晶体管。

10. 发明申请

US20060221727A1 Semiconductor memory device and semiconductor device 有权
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US20060221727A1
公开(公告)日：2006-10-05
申请号：US11391226
申请日：2006-03-29
申请人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
发明人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
IPC分类号： G11C7/00
CPC分类号： G11C29/023 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.
摘要翻译：提供了能够通过修整半导体器件的内部特性来提高产量的技术。半导体器件具有内部降压电路和其特性值（内部电压等）可变的内部升压电路，熔丝电路单元，输入并保持来自外部的信号的JTAG功能单元304 控制电路，其基于熔丝电路单元的输出信号和JTAG功能单元的输出信号进行逻辑运算，并且控制内部降压电路和内部升压电路的特性值基于控制电路的逻辑运算的结果。

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