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1. 发明授权

US4642486A Decoder circuit using transistors or diodes of different characteristics 失效
标题翻译：解码电路采用晶体管或二极管的不同特性
公开(公告)号：US4642486A
公开(公告)日：1987-02-10
申请号：US686660
申请日：1984-12-27
申请人： Noriyuki Honma , Hiroaki Nambu , Isao Yoshida , Hisayuki Higuchi , Kunihiko Yamaguchi
发明人： Noriyuki Honma , Hiroaki Nambu , Isao Yoshida , Hisayuki Higuchi , Kunihiko Yamaguchi
IPC分类号： G11C11/413 , G11C11/34 , H03K17/60 , H03K17/62 , H03K19/013 , G11C8/00 , H03K19/082 , H03K19/092
CPC分类号： H03K17/603 , H03K17/6214
摘要： This invention is effective in the speeding up of a decoder circuit and maintenance of output amplitude. The invention is characterized in that, in a decoder circuit composed of a multi-emitter transistor or at least one diode group in which the anodes of a plurality of diodes are connected, and a charge circuit having an output emitter follower transistor, the multi-emitter transistor or the forward voltage of the diodes are larger than the voltage between the base and the emitter of the output emitter follower transistor.
摘要翻译：本发明在解码器电路的加速和输出振幅的维持方面是有效的。本发明的特征在于，在由多个发射极晶体管组成的解码器电路或连接有多个二极管的阳极的至少一个二极管组以及具有输出射极跟随器晶体管的充电电路的情况下，发射极晶体管或二极管的正向电压大于输出射极跟随器晶体管的基极和发射极之间的电压。

2. 发明授权

US5163022A Semiconductor cell memory with current sensing 失效
标题翻译：具有电流检测功能的半导体单元存储器
公开(公告)号：US5163022A
公开(公告)日：1992-11-10
申请号：US827873
申请日：1992-01-30
申请人： Noriyuki Homma , Hiroaki Nambu , Kunihiko Yamaguchi , Tohru Nakamura , Youji Idei , Kazuo Kanetani , Kenichi Ohhata , Yoshiaki Sakurai , Hisayuki Higuchi
发明人： Noriyuki Homma , Hiroaki Nambu , Kunihiko Yamaguchi , Tohru Nakamura , Youji Idei , Kazuo Kanetani , Kenichi Ohhata , Yoshiaki Sakurai , Hisayuki Higuchi
IPC分类号： G11C7/06 , G11C11/411 , G11C11/412 , G11C11/416 , G11C11/419
CPC分类号： G11C11/4113 , G11C11/412 , G11C11/416 , G11C11/419 , G11C7/062
摘要： The disclosure includes feeding a current I.sub.R to only BIT lines selected, or feeding current I.sub.R transiently to only the BIT lines switched from unselected to selected states; and a sense amplifier for detecting the difference between the currents flowing in selected BIT lines to read out stored information, wherein current I.sub.R and cell current I.sub.cell have a relation of I.sub.R >I.sub.cell. The BiC MOS memory has high speed, low power and high integration density. Diodes are provided between the memory cell and the BIT lines.
摘要翻译：本公开包括将电流IR馈送到仅选择的BIT线，或者将电流IR瞬时馈送到仅从未选择状态切换到选定状态的BIT线; 以及读出放大器，用于检测在所选择的BIT行中流动的电流之间的差以读出存储的信息，其中当前的IR和单元电流Icell具有IR> Icell的关系。 BiC MOS存储器具有高速度，低功耗和高集成度。在存储单元和BIT线之间提供二极管。

3. 发明授权

US5255225A Semiconductor integrated circuit device and memory consisting of semiconductor integrated circuit 失效
标题翻译：半导体集成电路器件和存储器由半导体集成电路组成
公开(公告)号：US5255225A
公开(公告)日：1993-10-19
申请号：US845557
申请日：1992-03-04
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
IPC分类号： G11C5/14 , G11C7/10 , G11C11/40
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided.A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor.The speed of an operation of the circuit device can be increased to a high level owing to a simple circuit in which a level, which is required to attain an output amplitude, of complementary output signals is secured by the current switch circuit, the amplified complementary signals being inputted into the emitter follower circuit to directly drive the output transistor.
摘要翻译：提供一种包括电平转换电路的半导体集成电路器件，其中电路的简化和操作速度的提高已经达到。通过包括接收输入信号和参考电压的差分晶体管的电流开关电路将被放大到所需信号电平的一对互补输出信号输入到一对发射极跟随器电路中。射极跟随器输出晶体管由来自一个射极跟随器电路的输出信号驱动，而在输出晶体管和用作负载的电流源之间提供的N沟道MOSFET由另一个射极跟随器电路的输出信号驱动到从输出晶体管的发射极获得电平放大的输出信号。电路装置的运行速度可以通过电流开关电路确保互补输出信号的达到输出幅度所需的电平的简单电路而增加到高电平，放大的互补信号被输入射极跟随器电路以直接驱动输出晶体管。

4. 发明授权

US5398201A Bit-line drive circuit for a semiconductor memory 失效
标题翻译：半导体存储器的位线驱动电路
公开(公告)号：US5398201A
公开(公告)日：1995-03-14
申请号：US53330
申请日：1993-04-28
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Hisayuki Higuchi , Kazuo Kanetani , Youji Idei , Ken'ichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Hisayuki Higuchi , Kazuo Kanetani , Youji Idei , Ken'ichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa
IPC分类号： G11C5/14 , G11C7/10 , G11C11/34
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished. The improvement of the drivers of word lines and bit lines is also disclosed and a semiconductor memory which can operate at a high speed as a whole semiconductor memory can be realized.
摘要翻译：一种适于实现存储器的高速的电路技术，其以使得存储器单元包括场效应晶体管和外围电路的方式构造，包括双极晶体管和场效应晶体管。根据本发明，将集电极连接到差分放大器并根据输入到基极或发射极的信号向差分放大器提供电流的双极晶体管和双极晶体管，以提供电流只有写入位线才能连接。根据本发明，通过切换选择位线来读取信息时的访问时间的高速度被实现。此外，当写入信息时位线的充电/放电时间减少，并且也可以实现高速的写入时间。还公开了字线和位线的驱动器的改进，并且可以实现可以作为整个半导体存储器以高速度操作的半导体存储器。

5. 发明授权

US4986666A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4986666A
公开(公告)日：1991-01-22
申请号：US277261
申请日：1988-11-29
申请人： Noriyuki Homma , Hisayuki Higuchi , Yoji Idei , Hiroaki Nambu , Yoshiaki Sakurai
发明人： Noriyuki Homma , Hisayuki Higuchi , Yoji Idei , Hiroaki Nambu , Yoshiaki Sakurai
IPC分类号： G11C7/06 , G11C7/10 , G11C8/10 , G11C11/416
CPC分类号： G11C7/1057 , G11C11/416 , G11C7/062 , G11C7/065 , G11C7/1039 , G11C7/1051 , G11C8/10
摘要： A semiconductor memory device capable of operating at high speeds, and a sense circuit and a decoder circuit that can be suitably used for the memory device. A latch function is imparted to at least either one of the decoder circuit or the sense circuit in the semiconductor memory device.
摘要翻译：能够高速运行的半导体存储器件，以及适用于存储器件的读出电路和解码器电路。锁存功能被赋予半导体存储器件中的解码器电路或感测电路中的至少一个。

6. 发明授权

US4942555A Bi-MOS semiconductor memory having high soft error immunity 失效
标题翻译：具有高软误差抗扰度的Bi-MOS半导体存储器
公开(公告)号：US4942555A
公开(公告)日：1990-07-17
申请号：US376865
申请日：1989-07-07
申请人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma , Kiyoo Itoh
发明人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma , Kiyoo Itoh
IPC分类号： G11C11/418 , G11C11/419
CPC分类号： G11C11/418 , G11C11/419
摘要： A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memory cell connected to selected word line and data line pairs and a load device of the data line, an arrangement is provided for setting the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of a data transfer MOS transistor of the memory cell. The signal read out from the memory cell is then applied through the data line to a differential amplifier using the base or gate of a junction type transistor as its input. Particularly to set the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of the data transfer MOS transistor of the memory cell, a device having high driving capability such as a bipolar transistor is used as the load of the data line. The word line voltage is changed over to two stages so that the data line voltage V.sub.D and the word line voltage V.sub.W satisfy the relation V.sub.W V.sub.D +V.sub.TH in a write cycle (where V.sub.TH is the threshold voltage of NMOS inside the memory cell).
摘要翻译：提供了具有高可靠性的半导体存储器，并且特别地防止了由于光线的数据破坏等。在用于根据连接到所选字线的触发器型存储单元的晶体管与数据线对之间的导通率以及数据线的负载装置的导通比来检测存储器数据的半导体存储器中，提供了用于设置字线电压低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压。从存储单元读出的信号然后通过数据线施加到使用结型晶体管的基极或栅极作为其输入的差分放大器。特别是为了将字线电压设定为低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压，使用诸如双极型晶体管的具有高驱动能力的器件作为负载的数据线。字线电压转换为两级，使得数据线电压VD和字线电压VW在读周期中满足关系VW VD + VTH（其中VTH 是存储单元内的NMOS的阈值电压）。

7. 发明授权

US4640721A Method of forming bipolar transistors with graft base regions 失效
标题翻译：用接枝基区形成双极晶体管的方法
公开(公告)号：US4640721A
公开(公告)日：1987-02-03
申请号：US741525
申请日：1985-06-05
申请人： Keijiro Uehara , Hisayuki Higuchi , Akio Hayasaka
发明人： Keijiro Uehara , Hisayuki Higuchi , Akio Hayasaka
IPC分类号： H01L21/225 , H01L21/285 , H01L21/385
CPC分类号： H01L21/2257 , H01L21/28525
摘要： After an end part of a polycrystalline silicon film has been oxidized from an exposed side surface thereof, a silicon dioxide film formed is removed, and an opening thus provided is used for diffusing an impurity into a semiconductor substrate so as to form a graft base region.This measure is effective for fabricating a semiconductor device of small required area at high precision.
摘要翻译：在多晶硅膜的一部分已经从其暴露的侧表面氧化后，除去形成的二氧化硅膜，并且将这样设置的开口用于将杂质扩散到半导体衬底中以形成接枝基区。该措施对于以高精度制造所需面积小的半导体器件是有效的。

8. 发明授权

US06665209B2 Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system 有权
公开(公告)号：US06665209B2
公开(公告)日：2003-12-16
申请号：US10320516
申请日：2002-12-17
申请人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
发明人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
IPC分类号： G11C1100
CPC分类号： G11C7/18 , G06F12/0802 , G11C7/065
摘要： A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

9. 发明授权

US06342710B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06342710B1
公开(公告)日：2002-01-29
申请号：US09521957
申请日：2000-03-09
申请人： Hisayuki Higuchi , Suguru Tachibana , Koichiro Ishibashi , Keijiro Uehara
发明人： Hisayuki Higuchi , Suguru Tachibana , Koichiro Ishibashi , Keijiro Uehara
IPC分类号： H01L2976
CPC分类号： G11C11/5621 , G11C15/04
摘要： A semiconductor integrated circuit, particularly a circuit for a high-speed low-power-consumption table look-aside buffer mounted in a microprocessor LSI. The semiconductor integrated circuit is provided with field effect transistors for comparing inputted multibit data signals with stored data and a coincidence-detecting signal line (25) to which current is applied at least while the data signals are compared with stored data. When the data signals coincide with the stored data, the transistors (26) conduct. The number of transistors (26) is equal to that of the inputted data signals. The drains of the transistors (260 are connected in parallel, and the sources are also connected in parallel and supplied with a predetermined voltage. By the integrated circuit, whether or not the inputted data signals coincide with the stored data is detected by detecting the potential of the coincidence-detecting signal line (25) upon a change of the applied current.
摘要翻译：一种半导体集成电路，特别是用于安装在微处理器LSI中的用于高速低功耗表格旁路缓冲器的电路。半导体集成电路设置有用于将输入的多位数据信号与存储的数据进行比较的场效应晶体管和至少在数据信号与存储的数据进行比较时施加电流的符合检测信号线（25）。当数据信号与存储的数据一致时，晶体管（26）导通。晶体管（26）的数量等于输入的数据信号的数量。晶体管的漏极（260）并联连接，源极并联连接并以预定电压供电，通过集成电路，通过检测电位来检测输入的数据信号是否与存储的数据一致的一致检测信号线（25）。

10. 发明授权

US5128743A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5128743A
公开(公告)日：1992-07-07
申请号：US891174
申请日：1986-07-31
申请人： Yoichi Tamaki , Tokuo Kure , Akira Sato , Hisayuki Higuchi
发明人： Yoichi Tamaki , Tokuo Kure , Akira Sato , Hisayuki Higuchi
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/76232 , Y10S148/051 , Y10S148/085 , Y10S148/161 , Y10S148/168
摘要： A semiconductor device and the method of manufacturing the same are disclosed, the semiconductor device having a plurality of elements isolated by a groove having a gentle slope at the upper side wall, and a steep slope at the lower side wall. This groove provides low steps on its mouth and occupies a small area on the substrate, thus enabling an extremely high-density integrated circuit to be formed.
摘要翻译：公开了一种半导体器件及其制造方法，所述半导体器件具有通过在上侧壁具有缓和斜面的凹槽隔离的多个元件和在下侧壁处的陡峭斜坡。该槽在其口上提供低台阶并占据基板上的小面积，从而能够形成极高密度的集成电路。

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