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1. 发明授权

US07158396B2 CAM (content addressable memory) apparatus 有权
标题翻译： CAM（内容可寻址存储器）装置
公开(公告)号：US07158396B2
公开(公告)日：2007-01-02
申请号：US10723833
申请日：2003-11-26
申请人： Noel Hatsch , Winfried Kamp , Siegmar Köppe , Thomas Künemund , Heinz Söldner , Michel D'Argouges
发明人： Noel Hatsch , Winfried Kamp , Siegmar Köppe , Thomas Künemund , Heinz Söldner , Michel D'Argouges
IPC分类号： G11C15/00
CPC分类号： G06F7/02 , G06F2207/025 , G11C15/04
摘要： The present invention provides a CAM (content addressable memory) apparatus having: a first memory device (10) with a word line input (WL) and at least one storage node (12; 13) for storing a first bit of a data word; a second memory device (11) with a word line input (WL) and at least one storage node (14; 15) for storing a second bit of a data word; and a comparator device (16) for comparing the first and second stored bits with two precoded comparison bits fed via four inputs (20; 21; 22; 23) and for driving a hit node (17) in the event of the first stored bit corresponding to the first comparison bit and the second stored bit corresponding to the second comparison bit.
摘要翻译：本发明提供一种CAM（内容可寻址存储器）装置，其具有：具有字线输入（WL）的第一存储器件（10）和用于存储数据字的第一位的至少一个存储节点（12; 13）具有字线输入（WL）的第二存储器件（11）和用于存储数据字的第二位的至少一个存储节点（14; 15）以及比较器装置（16），用于将第一和第二存储位与经由四个输入（20; 21; 22; 23）馈送的两个预编码比较位进行比较，并且用于在第一个存储位的情况下驱动命中节点（17）对应于对应于第二比较位的第一比较位和第二存储位。

2. 发明授权

US06978290B2 Carry ripple adder 有权
标题翻译：携带纹波加法器
公开(公告)号：US06978290B2
公开(公告)日：2005-12-20
申请号：US10116851
申请日：2002-04-05
申请人： Joel Hatsch , Winfried Kamp , Siegmar Köppe , Ronald Künemund , Eva Lackerschmid , Heinz Söldner
发明人： Joel Hatsch , Winfried Kamp , Siegmar Köppe , Ronald Künemund , Eva Lackerschmid , Heinz Söldner
IPC分类号： G06F7/50 , G06F7/60
CPC分类号： G06F7/607
摘要： A carry ripple adder contains five first inputs for accepting five input bits having equal significance w that are to be summed and two second inputs for accepting two carry bits having the significance w. It also contains an output for a sum bit having the significance w and two outputs for two carry bits having the significances 2w and 4w.
摘要翻译：进位纹波加法器包含五个第一输入，用于接受具有相等的有效w的五个输入比特，并且两个第二输入用于接受具有重要性w的两个进位。它还包含一个具有重要性w的和位的输出和两个具有重要性2w和4w的进位位的两个输出。

3. 发明授权

US06977831B2 Content addressable memory cell 有权
标题翻译：内容可寻址存储单元
公开(公告)号：US06977831B2
公开(公告)日：2005-12-20
申请号：US10943701
申请日：2004-09-17
申请人： Joel Hatsch , Winfried Kamp , Thomas Künemund , Holger Sedlak , Heinz Söldner
发明人： Joel Hatsch , Winfried Kamp , Thomas Künemund , Holger Sedlak , Heinz Söldner
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is constructed from at least eight transistors, at least four transistors being arranged in a first circuit part and at least four transistors being arranged in a second circuit part and each of the circuit parts having at least two circuit branches.
摘要翻译：一个实施例提供了具有电连接到比较器单元的第一存储单元的内容可寻址存储单元。比较器单元由至少八个晶体管构成，至少四个晶体管布置在第一电路部分中，并且至少四个晶体管布置在第二电路部分中，并且每个电路部分具有至少两个电路分支。

4. 发明授权

US07509561B2 Parity checking circuit for continuous checking of the parity of a memory cell 有权
标题翻译：用于连续检查存储单元奇偶校验的奇偶校验电路
公开(公告)号：US07509561B2
公开(公告)日：2009-03-24
申请号：US11063953
申请日：2005-02-23
申请人： Winfried Kamp , Siegmar Köppe
发明人： Winfried Kamp , Siegmar Köppe
IPC分类号： H03M13/00
CPC分类号： G11C15/04 , G06F11/1048 , G11C15/00 , G11C2029/0411
摘要： A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload data word to be stored, with the parity checking circuit being formed from four transistors of the same conductance type. The parity checking circuit has a detector, which automatically detects the change in an information state of a memory cell. The detector is in the form of an automatic state device and has a number of catch latches.
摘要翻译：奇偶校验电路被设计用于可内容寻址存储器单元的连续奇偶校验，并且被配置为使得在奇偶校验期间，每个数据字的奇偶校验步骤的数量与原始有效载荷数据字中的位数相同存储奇偶校验电路由相同电导型的四个晶体管形成。奇偶校验电路具有检测器，其自动检测存储器单元的信息状态的变化。检测器是自动状态设备的形式，并具有多个锁存器。

5. 发明申请

US20100308863A1 Architecture of Function Blocks and Wirings in a Structured ASIC and Configurable Driver Cell of a Logic Cell Zone 审中-公开
标题翻译：结构化ASIC中的功能块和布线的结构以及逻辑单元区的可配置驱动单元
公开(公告)号：US20100308863A1
公开(公告)日：2010-12-09
申请号：US12780772
申请日：2010-05-14
申请人： Jörg Gliese , Winfried Kamp , Siegmar Köppe , Michael Scheppler
发明人： Jörg Gliese , Winfried Kamp , Siegmar Köppe , Michael Scheppler
IPC分类号： H03K19/177
CPC分类号： H03K19/1735 , H01L27/11807
摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.
摘要翻译：集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

6. 发明授权

US07755110B2 Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone 有权
标题翻译：逻辑单元区域的结构化ASIC和可配置驱动单元中的功能块和布线的架构
公开(公告)号：US07755110B2
公开(公告)日：2010-07-13
申请号：US11088506
申请日：2005-03-24
申请人： Jörg Gliese , Winfried Kamp , Siegmar Köppe , Michael Scheppler
发明人： Jörg Gliese , Winfried Kamp , Siegmar Köppe , Michael Scheppler
IPC分类号： H01L27/10
CPC分类号： H03K19/1735 , H01L27/11807
摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.
摘要翻译：集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

7. 发明授权

US08854866B2 Identification circuit and method for generating an identification bit 有权
标题翻译：用于产生识别位的识别电路和方法
公开(公告)号：US08854866B2
公开(公告)日：2014-10-07
申请号：US13163131
申请日：2011-06-17
申请人： Peter Huber , Winfried Kamp , Joel Hatsch , Michel d'Argouges , Siegmar Koeppe , Thomas Kuenemund
发明人： Peter Huber , Winfried Kamp , Joel Hatsch , Michel d'Argouges , Siegmar Koeppe , Thomas Kuenemund
IPC分类号： G11C11/00 , G06F21/72 , H04L9/08
CPC分类号： H04L9/0866 , G06F21/72
摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.
摘要翻译：半导体器件包括识别电路。识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。识别电路还包括用于存储单元的驱动电路。驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

8. 发明申请

US20120020145A1 Identification Circuit and Method for Generating an Identification Bit 有权
标题翻译：识别电路和产生识别位的方法
公开(公告)号：US20120020145A1
公开(公告)日：2012-01-26
申请号：US13163131
申请日：2011-06-17
申请人： Peter Huber , Winfried Kamp , Joel Hatsch , Michel d'Argouges , Siegmar Koeppe
发明人： Peter Huber , Winfried Kamp , Joel Hatsch , Michel d'Argouges , Siegmar Koeppe
IPC分类号： G11C11/40 , G11C8/08
CPC分类号： H04L9/0866 , G06F21/72
摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.
摘要翻译：半导体器件包括识别电路。识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。识别电路还包括用于存储单元的驱动电路。驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

9. 发明授权

US06735742B2 Method for optimizing a cell layout using parameterizable cells and cell configuration data 有权
标题翻译：使用可参数化单元格和单元配置数据优化单元布局的方法
公开(公告)号：US06735742B2
公开(公告)日：2004-05-11
申请号：US09864979
申请日：2001-05-24
申请人： Joel Hatsch , Winfried Kamp , Ronald Künemund , Eva Lackerschmid , Heinz Söldner
发明人： Joel Hatsch , Winfried Kamp , Ronald Künemund , Eva Lackerschmid , Heinz Söldner
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5068 , H01L27/0207 , H01L27/118
摘要： A method for optimizing the layout of cells of an integrated circuit includes providing a cell-based network list with references to cell definitions with parameterizable dimensions, calculating a layout of an integrated circuit using the cell-based network list, extracting a primary network list from the layout, optimizing the component dimensions of at least some of the components of the integrated circuit using at least one predetermined optimization parameter and a simulation using the primary network list, creating an optimized secondary network list using the results of the component optimization, and automatically modifying the layout with respect to cell dimensions using a secondary network list.
摘要翻译：一种用于优化集成电路的单元布局的方法包括：提供具有可参数化维度的单元定义的参考的基于单元的网络列表，使用基于单元的网络列表计算集成电路的布局，从布局，使用至少一个预定的优化参数和使用主网络列表的模拟来优化集成电路的至少一些组件的组件尺寸，使用组件优化的结果创建优化的辅助网络列表，并且自动地使用辅助网络列表修改关于单元格尺寸的布局。

10. 发明授权

US07876893B2 Logic circuit and method for calculating an encrypted result operand 有权
标题翻译：用于计算加密结果操作数的逻辑电路和方法
公开(公告)号：US07876893B2
公开(公告)日：2011-01-25
申请号：US11462144
申请日：2006-08-03
申请人： Antoine Degrendel , Winfried Kamp , Manfred Roth , Thomas Kodytek
发明人： Antoine Degrendel , Winfried Kamp , Manfred Roth , Thomas Kodytek
IPC分类号： H04L9/28
CPC分类号： H03K19/0948 , G06F7/00 , G06F21/755 , G06F2207/7238 , G06F2207/7266
摘要： A logic circuit for calculating an encrypted dual-rail result operand from encrypted dual-rail input operands according to a combination rule includes inputs for receiving the input operands and an output for outputting the encrypted result operand. Each operand may comprise a first logic state or a second logic state. The logic circuit comprises a first logic stage connected between the inputs and an intermediate node and a second logic stage connected between the intermediate node and the output. The logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to maintain or change exactly once the logic state of the encrypted result operand, independently of an order of arrival of the encrypted input operands, depending on the combination rule, in order to impress the calculated first logic state or second logic state on the output.
摘要翻译：用于根据组合规则从加密的双轨输入操作数计算加密的双轨结果操作数的逻辑电路包括用于接收输入操作数的输入和用于输出加密结果操作数的输出。每个操作数可以包括第一逻辑状态或第二逻辑状态。逻辑电路包括连接在输入与中间节点之间的第一逻辑级和连接在中间节点与输出之间的第二逻辑级。逻辑级被形成为根据组合规则从输入操作数计算加密结果操作数的第一或第二逻辑状态，并且只要一旦加密结果操作数的逻辑状态独立于维护或更改加密的输入操作数，取决于组合规则，以便将计算出的第一逻辑状态或第二逻辑状态置于输出上。

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