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1. 发明授权

US07158396B2 CAM (content addressable memory) apparatus 有权
标题翻译： CAM（内容可寻址存储器）装置
公开(公告)号：US07158396B2
公开(公告)日：2007-01-02
申请号：US10723833
申请日：2003-11-26
申请人： Noel Hatsch , Winfried Kamp , Siegmar Köppe , Thomas Künemund , Heinz Söldner , Michel D'Argouges
发明人： Noel Hatsch , Winfried Kamp , Siegmar Köppe , Thomas Künemund , Heinz Söldner , Michel D'Argouges
IPC分类号： G11C15/00
CPC分类号： G06F7/02 , G06F2207/025 , G11C15/04
摘要： The present invention provides a CAM (content addressable memory) apparatus having: a first memory device (10) with a word line input (WL) and at least one storage node (12; 13) for storing a first bit of a data word; a second memory device (11) with a word line input (WL) and at least one storage node (14; 15) for storing a second bit of a data word; and a comparator device (16) for comparing the first and second stored bits with two precoded comparison bits fed via four inputs (20; 21; 22; 23) and for driving a hit node (17) in the event of the first stored bit corresponding to the first comparison bit and the second stored bit corresponding to the second comparison bit.
摘要翻译：本发明提供一种CAM（内容可寻址存储器）装置，其具有：具有字线输入（WL）的第一存储器件（10）和用于存储数据字的第一位的至少一个存储节点（12; 13）具有字线输入（WL）的第二存储器件（11）和用于存储数据字的第二位的至少一个存储节点（14; 15）以及比较器装置（16），用于将第一和第二存储位与经由四个输入（20; 21; 22; 23）馈送的两个预编码比较位进行比较，并且用于在第一个存储位的情况下驱动命中节点（17）对应于对应于第二比较位的第一比较位和第二存储位。

2. 发明授权

US06977831B2 Content addressable memory cell 有权
标题翻译：内容可寻址存储单元
公开(公告)号：US06977831B2
公开(公告)日：2005-12-20
申请号：US10943701
申请日：2004-09-17
申请人： Joel Hatsch , Winfried Kamp , Thomas Künemund , Holger Sedlak , Heinz Söldner
发明人： Joel Hatsch , Winfried Kamp , Thomas Künemund , Holger Sedlak , Heinz Söldner
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is constructed from at least eight transistors, at least four transistors being arranged in a first circuit part and at least four transistors being arranged in a second circuit part and each of the circuit parts having at least two circuit branches.
摘要翻译：一个实施例提供了具有电连接到比较器单元的第一存储单元的内容可寻址存储单元。比较器单元由至少八个晶体管构成，至少四个晶体管布置在第一电路部分中，并且至少四个晶体管布置在第二电路部分中，并且每个电路部分具有至少两个电路分支。

3. 发明授权

US06310494B1 Bus driver 有权
标题翻译：公车司机
公开(公告)号：US06310494B1
公开(公告)日：2001-10-30
申请号：US09243831
申请日：1999-02-01
申请人： Thomas Ehben , Thomas Steinecke , Dirk Römer , Thomas Künemund
发明人： Thomas Ehben , Thomas Steinecke , Dirk Römer , Thomas Künemund
IPC分类号： H03K190175
CPC分类号： H04L25/08 , H03K19/00346 , H03K19/00369
摘要： The invention relates to a bus driver having an inverter for driving a preferably clocked signal on a bus line. In the event of a capacitive coupling of the bus line to at least one neighboring bus line, a number of secondary inverters corresponding to the number of capacitively coupled bus lines are connected in parallel with the inverter of the bus driver. A simple logic combination supplies the necessary activating signals for the parallel connection of the secondary inverters. As a result, an additional secondary inverter can be connected in when an opposite edge occurs on a neighboring line for the instant of the edge. The invention consequently enables the driver intensity to be adapted dynamically to the signals of neighboring capacitively coupled bus lines.
摘要翻译：本发明涉及具有用于在总线上驱动优选时钟信号的反相器的总线驱动器。在总线线路与至少一个相邻总线电容耦合的情况下，与总线驱动器的反相器并联连接多个对应于电容耦合总线线路的次级逆变器。简单的逻辑组合为次级逆变器的并联提供必要的激活信号。结果，当相邻边缘发生相对边缘的边缘瞬间时，可以连接附加的次级逆变器。因此，本发明使驱动器强度能够动态地适应于相邻的电容耦合总线的信号。

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