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1. 发明授权

US08854866B2 Identification circuit and method for generating an identification bit 有权
标题翻译：用于产生识别位的识别电路和方法
公开(公告)号：US08854866B2
公开(公告)日：2014-10-07
申请号：US13163131
申请日：2011-06-17
申请人： Peter Huber , Winfried Kamp , Joel Hatsch , Michel d'Argouges , Siegmar Koeppe , Thomas Kuenemund
发明人： Peter Huber , Winfried Kamp , Joel Hatsch , Michel d'Argouges , Siegmar Koeppe , Thomas Kuenemund
IPC分类号： G11C11/00 , G06F21/72 , H04L9/08
CPC分类号： H04L9/0866 , G06F21/72
摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.
摘要翻译：半导体器件包括识别电路。识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。识别电路还包括用于存储单元的驱动电路。驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

2. 发明申请

US20070171099A1 CIRCUIT ARRANGEMENT AND METHOD FOR RECOGNIZING MANIPULATION ATTEMPTS 有权
标题翻译：电路布置和识别操作手段的方法
公开(公告)号：US20070171099A1
公开(公告)日：2007-07-26
申请号：US11561184
申请日：2006-11-17
申请人： Thomas Kuenemund
发明人： Thomas Kuenemund
IPC分类号： H03M7/00
CPC分类号： G06F21/75
摘要： A circuit arrangement having complementary data lines of a dual rail data bus, wherein in a regular operating phase the complementary data lines carry complementary signals, and in a precharge phase the complementary data lines assume an identical logic state or the same electrical potential. The circuit arrangement also has a device for detecting manipulation attempts, the device having a detector circuit, which outputs an alarm signal upon the occurrence of an identical logic state on both data lines in the regular operating phase.
摘要翻译：具有双轨数据总线的互补数据线的电路装置，其中在常规工作阶段中，互补数据线承载互补信号，并且在预充电阶段，互补数据线呈现相同的逻辑状态或相同的电位。电路装置还具有用于检测操作尝试的装置，该装置具有检测器电路，其在正常操作阶段中在两条数据线上发生相同逻辑状态时输出报警信号。

3. 发明授权

US08726123B2 Bit error correction for removing age related errors in a bit pattern 有权
标题翻译：用于消除位模式中的年龄相关错误的位纠错
公开(公告)号：US08726123B2
公开(公告)日：2014-05-13
申请号：US13548462
申请日：2012-07-13
申请人： Rainer Goettfert , Berndt Gammel , Thomas Kuenemund
发明人： Rainer Goettfert , Berndt Gammel , Thomas Kuenemund
IPC分类号： H03M13/00
CPC分类号： G06F11/10 , G06F11/1008 , G06F21/35 , G06F21/72 , H03M13/05 , H03M13/63 , H04L9/0866 , H04L2209/34
摘要： A bit error corrector includes an aging bit pattern memory operable to store at least one aging bit pattern which conveys aging-related effects within a succession of uncorrected bit patterns, a bit pattern modifier operable to modify a current, uncorrected bit pattern using the at least one aging bit pattern and generate a modified bit pattern, and a bit pattern comparator operable to compare the current uncorrected bit pattern with a corrected bit pattern which is based on the modified bit pattern and determine a corresponding comparative bit pattern. An aging bit pattern determiner is operable to recursively determine a new aging bit pattern based on the at least one aging bit pattern and the comparative bit pattern, and store the new aging bit pattern in the aging bit pattern memory for use during modification of a subsequent uncorrected bit pattern by the bit pattern modifier.
摘要翻译：位错误校正器包括老化位模式存储器，其可操作以存储在一系列未校正位模式中传达与老化有关的效应的至少一个老化位模式，位模式修改器可操作以使用至少一个修正的未校正位模式一个老化比特模式并产生修改的比特模式，以及比特模式比较器，用于将当前未校正比特模式与基于修改的比特模式的校正比特模式进行比较，并确定相应的比较比特模式。老化位模式确定器可操作以基于至少一个老化位模式和比较位模式递归地确定新的老化位模式，并将新的老化位模式存储在老化位模式存储器中，以在后续修改期间使用未校正的位模式由位模式修改器。

4. 发明授权

US08334707B2 Storage circuit with fault detection and method for operating the same 有权
标题翻译：具有故障检测的存储电路及其操作方法
公开(公告)号：US08334707B2
公开(公告)日：2012-12-18
申请号：US12344916
申请日：2008-12-29
申请人： Thomas Kuenemund
发明人： Thomas Kuenemund
IPC分类号： G06F7/38 , G06F7/04 , G06F17/30 , H03K19/00 , H03L7/00
CPC分类号： G11C7/24
摘要： Some embodiments show a storage circuit with fault detection. The storage circuit comprises, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state. Furthermore the storage circuit comprises a data input, a circuitry configured to cause the first fault detection circuit to assume the first stable state and the second fault detection circuit to assume the second stable state to store a data signal applied to the data input and a first output indicative of the state of the first fault detection circuit and a second output indicative of the state of the second fault detection circuit, wherein an invalid combination of the signal states at the first and second outputs indicate a fault.
摘要翻译：一些实施例示出了具有故障检测的存储电路。存储电路包括第一和第二故障检测电路，每个包括第一稳定状态和第二稳定状态，其中第一和第二故障检测电路中的每一个被配置为使得从第一稳定状态引起切换所需的故障信号强度状态到第二稳定状态不同于使从第二稳定状态切换到第一稳定状态所需的故障信号强度。此外，存储电路包括数据输入端，被配置为使第一故障检测电路呈现第一稳定状态的电路，而第二故障检测电路采用第二稳定状态以存储施加到数据输入端的数据信号;以及第一输出表示第一故障检测电路的状态的第二输出和指示第二故障检测电路的状态的第二输出，其中在第一和第二输出处的信号状态的无效组合指示故障。

5. 发明授权

US08135767B2 Standard cell for arithmetic logic unit and chip card controller 有权
标题翻译：用于算术逻辑单元和芯片卡控制器的标准单元
公开(公告)号：US08135767B2
公开(公告)日：2012-03-13
申请号：US11890966
申请日：2007-08-08
申请人： Thomas Kuenemund
发明人： Thomas Kuenemund
IPC分类号： G06F7/38 , G06F7/52
CPC分类号： G06F7/5016 , G06F7/764
摘要： A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.
摘要翻译：用于算术逻辑单元的单元包括第一输入; 第二个输入输入输入; 第一控制输入和第二控制输入; 以及连接到第一输入端，第二输入端，进位输入端，第一控制输入端和第二控制输入端的电路。该电路具有第一输出和第二输出，当第一控制输入和第二控制输入的值等于进位时的值时，第二输出具有作为第一输入和第二输入的函数的第一值，并且当第一控制输入和第二控制输入处的值与进位输入处的值无关时具有作为第一输入和第二输入的函数的第二值。

6. 发明授权

US08130008B2 Integrated circuit with a radiation-sensitive thyristor structure 有权
标题翻译：具有辐射敏感晶闸管结构的集成电路
公开(公告)号：US08130008B2
公开(公告)日：2012-03-06
申请号：US12714678
申请日：2010-03-01
申请人： Thomas Kuenemund
发明人： Thomas Kuenemund
IPC分类号： G01R31/02
CPC分类号： H03K17/72 , G06F21/81 , G06F21/87 , H01L23/576 , H01L31/1113 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprises a circuit used for storing or processing data and a radiation-sensitive thyristor structure configured to conditionally short two power supply terminals of the integrated circuit. The thyristor structure is configured to turn on in response to a region of the thyristor structure being irradiated with radiation to which the thyristor structure is sensitive, in order to establish an electrically conductive connection between a first power supply terminal of the power supply terminals of the integrated circuit and a second power supply terminal of the power supply terminals of the integrated circuit. The thyristor structure is further configured so that a power density of the radiation needed for turning on the thyristor structure is lower than a power density of the radiation needed for a change of data of the circuit used for storing or processing data.
摘要翻译：集成电路包括用于存储或处理数据的电路和被配置为有条件地短路集成电路的两个电源端子的辐射敏感晶闸管结构。晶闸管结构被配置为响应于晶闸管结构的区域被可控硅结构敏感的辐射照射而导通，以便在所述晶闸管结构的电源端子的第一电源端子之间建立导电连接，集成电路和集成电路的电源端子的第二电源端子。晶闸管结构被进一步配置，使得用于导通晶闸管结构所需的辐射的功率密度低于用于存储或处理数据的电路的数据变化所需的辐射的功率密度。

7. 发明申请

US20110210782A1 Integrated Circuit with a Radiation-Sensitive Thyristor Structure 有权
标题翻译：具有辐射敏感晶闸管结构的集成电路
公开(公告)号：US20110210782A1
公开(公告)日：2011-09-01
申请号：US12714678
申请日：2010-03-01
申请人： Thomas Kuenemund
发明人： Thomas Kuenemund
IPC分类号： H03K17/74 , H05K1/00 , G06F21/02 , H03K17/78
CPC分类号： H03K17/72 , G06F21/81 , G06F21/87 , H01L23/576 , H01L31/1113 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprises a circuit used for storing or processing data and a radiation-sensitive thyristor structure configured to conditionally short two power supply terminals of the integrated circuit. The thyristor structure is configured to turn on in response to a region of the thyristor structure being irradiated with radiation to which the thyristor structure is sensitive, in order to establish an electrically conductive connection between a first power supply terminal of the power supply terminals of the integrated circuit and a second power supply terminal of the power supply terminals of the integrated circuit. The thyristor structure is further configured so that a power density of the radiation needed for turning on the thyristor structure is lower than a power density of the radiation needed for a change of data of the circuit used for storing or processing data.
摘要翻译：集成电路包括用于存储或处理数据的电路和被配置为有条件地短路集成电路的两个电源端子的辐射敏感晶闸管结构。晶闸管结构被配置为响应于晶闸管结构的区域被可控硅结构敏感的辐射照射而导通，以便在所述晶闸管结构的电源端子的第一电源端子之间建立导电连接，集成电路和集成电路的电源端子的第二电源端子。晶闸管结构被进一步配置，使得用于导通晶闸管结构所需的辐射的功率密度低于用于存储或处理数据的电路的数据变化所需的辐射的功率密度。

8. 发明授权

US07898836B2 Masked memory cells 有权
标题翻译：屏蔽记忆体
公开(公告)号：US07898836B2
公开(公告)日：2011-03-01
申请号：US12106927
申请日：2008-04-21
申请人： Thomas Kuenemund , Karl Zapf , Artur Wroblewski
发明人： Thomas Kuenemund , Karl Zapf , Artur Wroblewski
IPC分类号： G11C17/00
CPC分类号： G11C17/12 , G11C17/18
摘要： An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.
摘要翻译：一种掩蔽存储单元的阵列，包括第一列中的第一存储单元和第二不同列中的第二存储单元，其中第一存储单元能够被访问，以便根据第一二进制掩码信号输出，在第一输出处的第一二进制值和第二输出处的第二二进制值，反之亦然，其中第二存储器单元能够被访问，以便根据第二二进制掩码信号输出第二二进制值第三输出和第二二进制值在第四输出或反之亦然，并且其中存储器单元的第二和第三输出连接到存储器阵列的相同位线。

9. 发明申请

US20090323439A1 MEMORY FOR STORING A BINARY STATE 有权
标题翻译：存储二进制状态的记忆
公开(公告)号：US20090323439A1
公开(公告)日：2009-12-31
申请号：US12106640
申请日：2008-04-21
申请人： Thomas Kuenemund
发明人： Thomas Kuenemund
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C8/16
摘要： A memory cell for storing a binary state, the memory cell being adapted for storing a binary state based on a write indication and a binary write masking value and for storing a complementary binary state based on the write indication and a complementary binary write masking value.
摘要翻译：一种用于存储二进制状态的存储器单元，所述存储器单元适于基于写入指示和二进制写入掩蔽值存储二进制状态，并且用于基于所述写入指示和互补的二进制写入掩蔽值来存储互补的二进制状态。

10. 发明授权

US08502585B2 Device with a data retention mode and a data processing mode 有权
标题翻译：具有数据保留模式和数据处理模式的设备
公开(公告)号：US08502585B2
公开(公告)日：2013-08-06
申请号：US13187772
申请日：2011-07-21
申请人： Thomas Kuenemund , Anton Huber , Roswitha Deppe
发明人： Thomas Kuenemund , Anton Huber , Roswitha Deppe
IPC分类号： H03K3/356
CPC分类号： H03K3/35625 , H03K3/356008 , H03K3/356156
摘要： A device includes a flip flop and a control circuit. The flip flop includes a flip flop data input terminal and a flip flop clock input terminal. The control circuit includes a control circuit data input terminal and a control circuit clock input terminal. The control circuit is configured to route, in a Data Processing Mode of the device, an incoming data signal from the control circuit data input terminal to the flip flop data input terminal and an incoming clock signal from the control circuit clock input terminal to the flip flop clock input terminal and to apply, in a Data Retention Mode of the device, a first given fixed signal value to the flip flop data input terminal independent of a value of the incoming data signal and a second given fixed signal value to the flip flop clock input terminal independent of a value of the incoming clock signal.
摘要翻译：一种装置包括触发器和控制电路。触发器包括触发器数据输入端和触发器时钟输入端。控制电路包括控制电路数据输入端和控制电路时钟输入端。控制电路被配置为在设备的数据处理模式中路由从控制电路数据输入端到触发器数据输入端的输入数据信号和从控制电路时钟输入端到触发器的输入时钟信号并且在设备的数据保留模式中，将与输入数据信号的值无关的触发器数据输入端的第一给定固定信号值和向触发器的第二给定固定信号值应用于触发器时钟输入端时钟输入端子独立于输入时钟信号的值。

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