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1. 发明授权

US08719827B2 Processor and program execution method capable of efficient program execution 有权
标题翻译：处理器和程序执行方法能够高效地执行程序
公开(公告)号：US08719827B2
公开(公告)日：2014-05-06
申请号：US13179614
申请日：2011-07-11
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/46 , G06F9/00 , G06F1/00
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要翻译：一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

2. 发明申请

US20100318707A1 EXTERNAL DEVICE ACCESS APPARATUS, CONTROL METHOD THEREOF, AND SYSTEM LSI 审中-公开
标题翻译：外部设备访问装置，其控制方法和系统LSI
公开(公告)号：US20100318707A1
公开(公告)日：2010-12-16
申请号：US12866061
申请日：2008-08-13
申请人： Tsuyoshi Tanaka , Nobuo Higaki , Takasi Inoue , Yosuke Kudo , Kazushi Kurata
发明人： Tsuyoshi Tanaka , Nobuo Higaki , Takasi Inoue , Yosuke Kudo , Kazushi Kurata
IPC分类号： G06F13/24 , G06F9/30
CPC分类号： G06F13/385 , G06F3/0611 , G06F3/0656 , G06F3/0659 , G06F3/0683
摘要： An external device access apparatus according to the present invention includes: an address control unit that accepts a prefetch request and a prefetch data readout request from a master and performs a prefetch operation and a prefetch data readout operation; a readout data storage unit that stores data read out through the prefetch operation; a storage operation status holding unit that holds a prefetch operation status indicating whether or not the prefetch operation has been completed; and an acceptance signal generation unit that outputs, to the master, an acceptance signal indicating that the prefetch data readout request has been accepted from the master. First information indicating a status of the prefetch operation is outputted to the master based on the prefetch operation status.
摘要翻译：根据本发明的外部设备接入装置包括：地址控制单元，其从主机接收预取请求和预取数据读出请求，并执行预取操作和预取数据读出操作; 读出数据存储单元，存储通过预取操作读出的数据; 存储操作状态保持单元，其保存指示预取操作是否已经完成的预取操作状态; 以及接收信号生成单元，其向主设备输出表示预取数据读出请求已经从主机接受的接收信号。基于预取操作状态，将指示预取操作的状态的第一信息输出到主机。

3. 发明授权

US07693514B2 Information gathering robot 有权
标题翻译：信息采集机器人
公开(公告)号：US07693514B2
公开(公告)日：2010-04-06
申请号：US10915535
申请日：2004-08-11
申请人： Yoshiaki Sakagami , Yoko Saito , Koji Kawabe , Takamichi Shimada , Nobuo Higaki
发明人： Yoshiaki Sakagami , Yoko Saito , Koji Kawabe , Takamichi Shimada , Nobuo Higaki
IPC分类号： H04Q7/20
CPC分类号： H04W4/02 , G05D1/0246 , G05D1/0274 , G05D2201/0207 , H04L67/12
摘要： In an event site or the like, a visitor may waste time and effort trying to find a spot where an event of interest may be taking place because the visitor is unable to look through the entire site from any particular spot. An information gathering robot roams in such an event site typically along a prescribed route, and notes spots of interest to transmit this information to a data server. The visitor can access the data server to find a spot of interest of his or her choice substantially on a real time basis.
摘要翻译：在事件现场等中，访客可能会浪费时间和精力去尝试寻找可能发生的兴趣事件的地点，因为访问者无法从任何特定的地点查看整个站点。信息收集机器人通常沿着规定的路线在这样的事件站点中漫游，并且记录将该信息发送到数据服务器的感兴趣点。访问者可以访问数据服务器，实质上基于实时地查找他或她选择的兴趣点。

4. 发明申请

US20080267286A1 Image Encoding Device and Method 审中-公开
标题翻译：图像编码装置及方法
公开(公告)号：US20080267286A1
公开(公告)日：2008-10-30
申请号：US11572680
申请日：2005-02-23
申请人： Hideki Kuroki , Shigeki Fujii , Akihiko Ootani , Nobuo Higaki
发明人： Hideki Kuroki , Shigeki Fujii , Akihiko Ootani , Nobuo Higaki
IPC分类号： H04N7/12 , H04N7/32
CPC分类号： H04N19/00 , H04N19/11 , H04N19/136 , H04N19/157 , H04N19/176
摘要： An image encoding device includes a prediction processing unit which performs prediction processing on m components among N components which constitute a quantized block; a first Coded Block Pattern (CBP) judging unit which judges whether or not (N−m) components include a non-zero component in a first operation mode, and whether or not (N−n) components include a non-zero component in a second operation mode; a second CBP judging unit which judges whether or not the m components on which the prediction processing has been performed include a non-zero component in the first operation mode, and whether or not n components include a non-zero component in the second operation mode; and a CBP generating unit which generates a CBP code indicating whether or not all the components of the block are 0 components based on the judgments made by the first and second judging units.
摘要翻译：图像编码装置包括对构成量化块的N个成分中的m个成分进行预测处理的预测处理部; 第一编码块模式（CBP）判断单元，判定在第一操作模式中（Nm）分量是否包括非零分量，以及（Nn）分量是否包括第二操作模式中的非零分量 ; 第二CBP判断单元，判断在其中执行了预测处理的m个分量是否包括第一操作模式中的非零分量，以及n个分量是否包括第二操作模式中的非零分量 ; 以及CBP生成单元，其基于由所述第一判断单元和所述第二判断单元进行的判断，生成表示所述块的全部成分是否为0成分的CBP码。

5. 发明授权

US07386707B2 Processor and program execution method capable of efficient program execution 有权
标题翻译：处理器和程序执行方法能够高效地执行程序
公开(公告)号：US07386707B2
公开(公告)日：2008-06-10
申请号：US10338408
申请日：2003-01-08
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要翻译：一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

6. 发明授权

US07340100B2 Posture recognition apparatus and autonomous robot 有权
标题翻译：姿势识别装置和自主机器人
公开(公告)号：US07340100B2
公开(公告)日：2008-03-04
申请号：US10635778
申请日：2003-08-07
申请人： Nobuo Higaki , Yoshiaki Sakagami , Naoaki Sumida
发明人： Nobuo Higaki , Yoshiaki Sakagami , Naoaki Sumida
IPC分类号： G06K9/48
CPC分类号： G06F3/017 , G06K9/00335
摘要： A posture recognition apparatus recognizes instructions signified by postures of persons present in the surroundings, from images obtained with an image capture device. The posture recognition apparatus includes an outline extraction device that extracts an outline of a body which is a candidate for a person from the images; a distance calculation device that calculates a distance to the body being the candidate, from distance information of each pixel within the outline in the image; a search device that searches for a candidate for a hand of a person based on the outline and the distance to the body represented by the outline; and a posture determination device that determines an instruction corresponding to the relative position of the candidate for a hand and the outline, and outputs this determination result as a posture determination result.
摘要翻译：姿势识别装置从通过图像拍摄装置获得的图像识别由周围的人存在的姿势所指示的指令。姿势识别装置包括：轮廓提取装置，从图像中提取作为人的候选者的身体的轮廓; 距离计算装置，从图像中的轮廓内的每个像素的距离信息计算到作为候选者的身体的距离; 搜索装置，其基于轮廓和与轮廓所表示的身体的距离来搜索人的手的候选人; 以及姿势确定装置，其确定与手的候选者和轮廓的相对位置相对应的指令，并将该确定结果作为姿势确定结果输出。

7. 发明授权

US07305499B2 DMA controller for controlling and measuring the bus occupation time value for a plurality of DMA transfers 有权
标题翻译： DMA控制器，用于控制和测量多个DMA传输的总线占用时间值
公开(公告)号：US07305499B2
公开(公告)日：2007-12-04
申请号：US10901294
申请日：2004-07-29
申请人： Akihiro Furuta , Nobuo Higaki , Tetsuya Tanaka , Tsuneyuki Suzuki
发明人： Akihiro Furuta , Nobuo Higaki , Tetsuya Tanaka , Tsuneyuki Suzuki
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a data transfer performing unit for performing the DMA transfer on the basis of the DMA transfer parameters; a control unit for controlling the receive and transmit of the DMA transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapse time when a first DMA transfer is started for each of the logical processors. When the bus occupation elapse time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is currently performed to start the DMA transfers based on the transfer parameters related to the logical processors of a prescribed sequence.
摘要翻译：本发明提供一种DMA传输控制器，包括：传输参数存储单元，用于存储总线占用时间值，并为多个逻辑处理器中的每一个传送一组或多组DMA传输的参数; 数据传送执行单元，用于基于DMA传输参数执行DMA传输; 控制单元，用于控制DMA传输参数的接收和发送以及DMA传输的开始和中断; 以及时间测量单元，用于当为每个逻辑处理器启动第一个DMA传输时开始测量总线占用时间。当总线占用时间达到总线占用时间值时，控制单元基于与规定序列的逻辑处理器相关的传输参数中断当前执行的DMA传输以开始DMA传输。

8. 发明申请

US20070086656A1 Contour extraction apparatus, contour extraction method, and contour extraction program 有权
标题翻译：轮廓提取装置，轮廓提取方法和轮廓提取程序
公开(公告)号：US20070086656A1
公开(公告)日：2007-04-19
申请号：US10563064
申请日：2004-07-01
申请人： Nobuo Higaki
发明人： Nobuo Higaki
IPC分类号： G06K9/48
CPC分类号： G06K9/48 , G06K9/6207 , G06T7/12 , G06T7/149
摘要： To provide a contour extraction apparatus which can perform much more quickly the contour division when required while reducing the cost for computing. In contour extraction unit 32: a plurality of nodes are located on a periphery of the target object by the node locator 32A; the contour, which is formed by connecting nodes at a predetermined connection order, is deformed by the contour deformation unit 32B; an internode distance about all combination of nodes excepting the inter node distance between adjacent nodes is computed by the internode distance calculator 32C; it is checked by the connection creator 32D whether or not the combination of nodes whose internode distance is below a first threshold value exists, a connection line to divide the contour is created, the connection line connects one of nodes in the combination with the node adjacent to the other node in the combination, and the node adjacent to the other node is the node being positioning upstream or downstream in the predetermined connection order with respect to the other node.
摘要翻译：提供一种轮廓提取装置，其可以在需要时更快地执行轮廓划分，同时降低计算成本。在轮廓提取单元32中：多个节点由节点定位器32A位于目标对象的外围; 由轮廓变形部32B变形由连接节点以规定的连接顺序形成的轮廓，通过节间距离计算器32C计算关于除了相邻节点之间的节间距离之外的节点的所有组合的节间距离; 由连接创建器32D检查是否存在节间距离低于第一阈值的节点的组合，创建用于划分轮廓的连接线，连接线将组合中的节点之一连接到节点并且与其他节点相邻的节点是相对于另一个节点以预定连接顺序定位在上游或下游的节点。

9. 发明授权

US06920248B2 Contour detecting apparatus and method, and storage medium storing contour detecting program 失效
标题翻译：轮廓检测装置和方法，以及存储轮廓检测程序的存储介质
公开(公告)号：US06920248B2
公开(公告)日：2005-07-19
申请号：US09951540
申请日：2001-09-14
申请人： Nobuo Higaki
发明人： Nobuo Higaki
IPC分类号： G06T7/60 , G06K9/48 , G06T5/00 , G06K9/46
CPC分类号： G06K9/48 , G06T7/12 , G06T2207/10048
摘要： A contour detecting apparatus for accurately detecting a contour of a target object without increasing the detection time is disclosed. The apparatus comprises a section for storing a contour model consisting of nodes, which surrounds at least one target object in a captured image and is used for detecting a contour of the target object; a deforming section for contracting or expanding the contour model by shifting the nodes based on a predetermined rule; a section for calculating a distance between two non-adjacent nodes of the contour model which was deformed by the deforming section, and determining that the contour model is to be split when the calculated distance is equal to or smaller than a predetermined threshold; and a section for splitting the contour model according to a result of the above determination, wherein the splitting operation is executed in the vicinity of said non-adjacent nodes.
摘要翻译：公开了一种用于在不增加检测时间的情况下精确地检测目标对象的轮廓的轮廓检测装置。该装置包括用于存储由节点组成的轮廓模型的部分，其围绕捕获的图像中的至少一个目标对象并且用于检测目标对象的轮廓; 变形段，用于通过基于预定规则移动节点来收缩或扩展轮廓模型; 用于计算由变形部分变形的轮廓模型的两个不相邻节点之间的距离的部分，以及当所计算的距离等于或小于预定阈值时确定轮廓模型将被分割; 以及根据上述确定的结果分割轮廓模型的部分，其中在所述不相邻节点附近执行分割操作。

10. 发明授权

US06880150B1 PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND A DISASSEMBLER FOR SUCH PROCESSOR 有权
标题翻译：执行单元中指令的处理程序，与指令读取的单元相关，以及编译器，优化设备，汇编器，链接器，调试器和此类处理器的分解器
公开(公告)号：US06880150B1
公开(公告)日：2005-04-12
申请号：US09301284
申请日：1999-04-28
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当指令解码器409a〜409c解码分支指令时，分支指令中包含的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

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