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1. 发明授权

US4996659A Method of diagnosing integrated logic circuit 失效
标题翻译：诊断集成逻辑电路的方法
公开(公告)号：US4996659A
公开(公告)日：1991-02-26
申请号：US84153
申请日：1987-08-12
申请人： Noboru Yamaguchi , Hideo Nakamura , Yoshimune Hagiwara , Tsukasa Sato , Haruo Koizumi
发明人： Noboru Yamaguchi , Hideo Nakamura , Yoshimune Hagiwara , Tsukasa Sato , Haruo Koizumi
IPC分类号： G01R31/305 , G01R31/3193
CPC分类号： G01R31/3193 , G01R31/305
摘要： A method of diagnosis of an integrated logic circuit having function blocks, in which a test signal is supplied to the logic circuit; an input signal to and an output signal from at least one of the function blocks are detected by the use of a contactless probing device such as an electron beam probing device or laser beam probing device; simulation is carried out of a normal logic operation of the function block with the detected input signal to provide a simulated output signal; the detected and simulated output signals are compared with each other; and the function block is determined as being normal or abnormal according to the result of the comparison. When the function block includes plural logic elements, the cause of the abnormality may be traced back to a faulty function element by detecting the output of a function element by a contactless probing device, comparing the detected output with a corresponding simulated output and repeating the detection and comparison on other function elements in the function block until the comparison results in coincidence. The function element which receives the signal providing the coincidence as a result of the comparison is determined as the faulty function element.
摘要翻译：一种诊断具有功能块的集成逻辑电路的方法，其中测试信号被提供给逻辑电路; 通过使用诸如电子束探测装置或激光束探测装置的非接触探测装置来检测来自至少一个功能块的输入信号和输出信号; 利用检测到的输入信号对功能块的正常逻辑运算进行仿真，以提供模拟输出信号; 检测和模拟的输出信号相互比较; 并且根据比较的结果将功能块确定为正常或异常。当功能块包括多个逻辑元件时，通过非接触探测装置检测功能元件的输出，将检测到的输出与对应的模拟输出进行比较并重复检测，可以将异常的原因追溯到故障功能元件并比较功能块中的其他功能元素，直到比较结果重合。将作为比较结果提供一致的信号的功能元件确定为故障功能元件。

2. 发明授权

US4720811A Microprocessor capable of stopping its operation at any cycle time 失效
标题翻译：微处理器能够在任何周期时间内停止运行
公开(公告)号：US4720811A
公开(公告)日：1988-01-19
申请号：US855942
申请日：1986-04-25
申请人： Noboru Yamaguchi , Kunio Uchiyama , Haruo Koizumi , Yoshimune Hagiwara , Tadahiko Nishimukai
发明人： Noboru Yamaguchi , Kunio Uchiyama , Haruo Koizumi , Yoshimune Hagiwara , Tadahiko Nishimukai
IPC分类号： G06F11/07 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3648 , G06F11/0721 , G06F11/0766
摘要： Herein disclosed is a method of controlling a microprocessor in accordance with the present invention characterized in that, when the microprocessor for executing a microprogram in accordance with clock cycles .PHI..sub.1 and .PHI..sub.2 receives a command (i.e., STOP signal) for stopping a normal operation from the outside, a freezing signal (i.e., FRZ signal) synchronizing with the clock cycles is generated to bring the operation being executed into a stopped state.
摘要翻译：本文公开了一种根据本发明的微处理器的控制方法，其特征在于，当用于根据时钟周期PHI 1和PHI 2执行微程序的微处理器接收到用于停止正常操作的命令（即，停止信号）时从外部产生与时钟周期同步的冻结信号（即，FRZ信号），以使所执行的操作进入停止状态。

3. 发明授权

US5165086A Microprocessor chip using two-level metal lines technology 失效
标题翻译：微处理器芯片采用二级金属线技术
公开(公告)号：US5165086A
公开(公告)日：1992-11-17
申请号：US527866
申请日：1990-05-24
申请人： Shigehiro Kamejima , Yoshimune Hagiwara , Kouki Noguchi , Minoru Ishii , Tadahiko Nishimukai , Hideo Nakamura , Haruo Koizumi , Hiroyuki Masuda
发明人： Shigehiro Kamejima , Yoshimune Hagiwara , Kouki Noguchi , Minoru Ishii , Tadahiko Nishimukai , Hideo Nakamura , Haruo Koizumi , Hiroyuki Masuda
IPC分类号： H01L27/02
CPC分类号： H01L27/0207
摘要： A microprocessor chip including a ROM portion for storing a microprogram, an execution unit portion for executing an arithmetic operation and random logic circuits disposed between the ROM portion and the execution unit portion. Two-level metal lines technology is used for supplying power for grounding and for providing input/output interconnect lines for the random logic circuits.
摘要翻译：一种微处理器芯片，包括用于存储微程序的ROM部分，用于执行算术运算的执行单元部分和布置在ROM部分和执行单元部分之间的随机逻辑电路。两级金属线技术用于为接地提供电源，并为随机逻辑电路提供输入/输出互连线。

4. 发明授权

US4353030A Pulse frequency multiplier circuit 失效
标题翻译：脉冲倍频电路
公开(公告)号：US4353030A
公开(公告)日：1982-10-05
申请号：US184312
申请日：1980-09-05
申请人： Hideo Nakamura , Tsuneo Funabashi , Haruo Koizumi
发明人： Hideo Nakamura , Tsuneo Funabashi , Haruo Koizumi
IPC分类号： G06F7/68 , H03K5/00
CPC分类号： G06F7/68 , H03K5/00 , H03K5/00006
摘要： In a pulse frequency multiplying circuit, a first capacitor charged to a given potential is discharged through a first constant-current circuit during a period corresponding to a pulse width of a reference pulse. Then, the terminal voltage of the first capacitor is applied as a reference voltage to one input terminal of a comparator circuit. A triangle wave voltage formed by alternately discharging a pair of second capacitors charged to a given potential, through a second constant-current circuit with a current value n times that in the first constant-current circuit, is applied to the other input terminal of the comparator circuit. The output from the comparator circuit operates a flip-flop circuit. In accordance with the output signal, the charge/discharge operation of said second capacitors is switched, whereby said flip-flop circuit produces a pulse with a frequency n times that of the reference pulse.
摘要翻译：在脉冲倍频电路中，对应于给定电位的第一电容器在与参考脉冲的脉冲宽度对应的周期期间通过第一恒流电路放电。然后，将第一电容器的端子电压作为参考电压施加到比较器电路的一个输入端子。将通过电流值为n倍于第一恒定电流电路的第二恒定电流电路交替地放电到给定电位的一对第二电容器形成的三角波电压被施加到第一恒定电流电路的另一输入端子比较器电路。比较器电路的输出操作触发器电路。根据输出信号，切换所述第二电容器的充电/放电操作，由此所述触发器电路产生频率为参考脉冲的频率n倍的脉冲。

5. 发明授权

US07015905B2 Capacitive load driving circuit driving capacitive loads such as pixels in plasma display panels and plasma display apparatus having the capacitive load driving circuit 失效
标题翻译：驱动诸如等离子体显示面板中的像素的容性负载的电容负载驱动电路和具有电容性负载驱动电路的等离子体显示装置
公开(公告)号：US07015905B2
公开(公告)日：2006-03-21
申请号：US10759072
申请日：2004-01-20
申请人： Makoto Onozawa , Yoshinori Okada , Haruo Koizumi
发明人： Makoto Onozawa , Yoshinori Okada , Haruo Koizumi
IPC分类号： G09G5/00 , G09G3/10
CPC分类号： G09G3/2965 , G09G3/293 , G09G2310/0275 , G09G2330/024
摘要： A capacitive load driving circuit has an input terminal, a front-edge delay circuit, a back-edge delay circuit, an amplifying circuit, and an output switch device driven by the amplifying circuit. The front-edge delay circuit delays a front edge of an input signal input via the input terminal, the back-edge delay circuit delays a back edge of the input signal, and the amplifying circuit amplifies a drive control signal obtained through the front-edge delay circuit and the back-edge delay circuit.
摘要翻译：容性负载驱动电路具有由放大电路驱动的输入端子，前沿延迟电路，后沿延迟电路，放大电路和输出开关器件。前沿延迟电路延迟通过输入端子输入的输入信号的前沿，后沿延迟电路延迟输入信号的后沿，并且放大电路放大通过前沿获得的驱动控制信号延迟电路和后沿延迟电路。

6. 发明授权

US06885158B2 Plasma display apparatus with reduced voltage variation 失效
标题翻译：具有降低电压变化的等离子体显示装置
公开(公告)号：US06885158B2
公开(公告)日：2005-04-26
申请号：US10695132
申请日：2003-10-29
申请人： Makoto Onozawa , Haruo Koizumi
发明人： Makoto Onozawa , Haruo Koizumi
IPC分类号： H04N5/66 , G09F9/00 , G09G3/20 , G09G3/288 , G09G3/291 , G09G3/294 , G09G3/296 , G09G3/298 , G09G3/10
CPC分类号： G09G3/296 , G09G3/299 , G09G2320/0247
摘要： A plasma display apparatus includes a plurality of electrodes for electric discharge, and a drive circuit which drives the plurality of electrodes. The drive circuit includes first and second outputting circuits provided on a board, a connector provided on the board and coupled to the plurality of electrodes, and a conductive plate which is provided on the board, and provides electrical couplings between the first and second outputting circuits and the connector. The conductive plate includes a first area connected to the first outputting circuit and a second area connected to the second outputting circuit, the first area and the second area being substantially line-symmetric.
摘要翻译：等离子体显示装置包括多个用于放电的电极和驱动多个电极的驱动电路。驱动电路包括设置在电路板上的第一和第二输出电路，设置在电路板上并连接到多个电极的连接器和设置在电路板上的导电板，并且在第一和第二输出电路之间提供电耦合和连接器。导电板包括连接到第一输出电路的第一区域和连接到第二输出电路的第二区域，第一区域和第二区域基本上是线对称的。

7. 外观设计

USD502867S1 Container 失效
公开(公告)号：USD502867S1
公开(公告)日：2005-03-15
申请号：US29176791
申请日：2003-02-25
申请人： Haruo Koizumi
设计人： Haruo Koizumi

8. 发明授权

US06624798B1 Display apparatus with flat display panel 失效
标题翻译：具有平板显示面板的显示装置
公开(公告)号：US06624798B1
公开(公告)日：2003-09-23
申请号：US08816684
申请日：1997-03-13
申请人： Masami Aoki , Toyoshi Kawada , Haruo Koizumi
发明人： Masami Aoki , Toyoshi Kawada , Haruo Koizumi
IPC分类号： G09G328
CPC分类号： G09G3/296 , G09G3/2932 , G09G2310/0218 , G09G2310/066 , G09G2330/023
摘要： A plasma-display-panel display apparatus includes a flat display panel having a plurality of address electrodes and a plurality of scanning electrodes extending transversely to the address electrodes and disposed in confronting relation to the address electrodes with a discharge space defined therebetween. A scanning electrode driver successively supplies scanning pulses to the scanning electrodes with scanning timing, and an address driver supplies address pulses according to display data to the address electrodes in synchronism with the scanning timing. The address electrodes include first and second address electrodes disposed adjacent to each other. The address pulse applied to the first address electrode rises and the address pulse applied to the second address electrode falls with a predetermined time difference therebetween.
摘要翻译：等离子体显示面板显示装置包括具有多个寻址电极的平面显示面板和横向于寻址电极延伸的多个扫描电极，并且与地址电极相对地设置，其间限定有放电空间。扫描电极驱动器以扫描定时向扫描电极依次提供扫描脉冲，并且地址驱动器根据显示数据向寻址电极提供与扫描定时同步的寻址脉冲。寻址电极包括彼此相邻布置的第一和第二寻址电极。施加到第一寻址电极的地址脉冲上升，并且施加到第二寻址电极的寻址脉冲以其间的预定时间差落下。

9. 发明授权

US06301117B1 Tuner structure and cable modem tuner using the same 失效
标题翻译：调谐器结构和电缆调制解调器调谐器使用相同
公开(公告)号：US06301117B1
公开(公告)日：2001-10-09
申请号：US09548363
申请日：2000-04-12
申请人： Miyoshi Yamauchi , Mitsuhiro Noboru , Haruo Koizumi , Syuuji Matsuura , Toshifumi Akiyama
发明人： Miyoshi Yamauchi , Mitsuhiro Noboru , Haruo Koizumi , Syuuji Matsuura , Toshifumi Akiyama
IPC分类号： H05K714
CPC分类号： H05K9/006
摘要： The tuner structure of the present invention includes: a circuit board on which electronic circuit components such as transistors and resistors have been mounted; a chassis angle; and a shield cover. In the tuner structure, a feedthrough capacitor for inputting/outputting a power, a control signal and the like is mounted to a metal plate disposed in parallel to the circuit board.
摘要翻译：本发明的调谐器结构包括：其上安装有诸如晶体管和电阻器的电子电路部件的电路板; 底盘角度; 和屏蔽罩。在调谐器结构中，用于输入/输出功率的馈通电容器，控制信号等安装在与电路板平行设置的金属板上。

10. 发明申请

US20090284447A1 PLASMA DISPLAY APPARATUS 审中-公开
标题翻译：等离子显示设备
公开(公告)号：US20090284447A1
公开(公告)日：2009-11-19
申请号：US12306528
申请日：2006-09-04
申请人： Haruo Koizumi , Makoto Onozawa
发明人： Haruo Koizumi , Makoto Onozawa
IPC分类号： G09G3/28
CPC分类号： G09G3/296 , G09G2330/021 , G09G2330/028 , G09G2330/045
摘要： An object of the present invention is to reduce power consumption and heat generation in an A/S separating circuit for preventing an inflow of an auxiliary voltage into a sustain discharge voltage source in a Y electrode driver circuit or an X electrode driver circuit of a plasma display apparatus. In the present invention, a sustain-voltage generating circuit in the Y-electrode driver circuit or the X-electrode driver circuit is configured of a bidirectional switch, and the A/S separating circuit is removed.
摘要翻译：本发明的一个目的是降低A / S分离电路中的功耗和发热，以防止在Y电极驱动电路或等离子体的X电极驱动电路中将辅助电压流入维持放电电压源显示装置。在本发明中，Y电极驱动电路或X电极驱动电路中的维持电压产生电路由双向开关构成，去除了A / S分离电路。

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