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1. 发明授权

US4720811A Microprocessor capable of stopping its operation at any cycle time 失效
标题翻译：微处理器能够在任何周期时间内停止运行
公开(公告)号：US4720811A
公开(公告)日：1988-01-19
申请号：US855942
申请日：1986-04-25
申请人： Noboru Yamaguchi , Kunio Uchiyama , Haruo Koizumi , Yoshimune Hagiwara , Tadahiko Nishimukai
发明人： Noboru Yamaguchi , Kunio Uchiyama , Haruo Koizumi , Yoshimune Hagiwara , Tadahiko Nishimukai
IPC分类号： G06F11/07 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3648 , G06F11/0721 , G06F11/0766
摘要： Herein disclosed is a method of controlling a microprocessor in accordance with the present invention characterized in that, when the microprocessor for executing a microprogram in accordance with clock cycles .PHI..sub.1 and .PHI..sub.2 receives a command (i.e., STOP signal) for stopping a normal operation from the outside, a freezing signal (i.e., FRZ signal) synchronizing with the clock cycles is generated to bring the operation being executed into a stopped state.
摘要翻译：本文公开了一种根据本发明的微处理器的控制方法，其特征在于，当用于根据时钟周期PHI 1和PHI 2执行微程序的微处理器接收到用于停止正常操作的命令（即，停止信号）时从外部产生与时钟周期同步的冻结信号（即，FRZ信号），以使所执行的操作进入停止状态。

2. 发明授权

US06779102B2 Data processor capable of executing an instruction that makes a cache memory ineffective 失效
标题翻译：能够执行使高速缓冲存储器无效的指令的数据处理器
公开(公告)号：US06779102B2
公开(公告)日：2004-08-17
申请号：US09886267
申请日：2001-06-22
申请人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Ikuya Kawasaki , Makoto Hanawa
发明人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Ikuya Kawasaki , Makoto Hanawa
IPC分类号： G06F1578
CPC分类号： G06F9/30047 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0848 , G06F12/0891
摘要： A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the instruction address, an instruction decoder decoding an instruction from said cache memory corresponding to an instruction address from said instruction address generator, an operand address generator generating an operand address in response to an output signal of said instruction decoder, and an operand cache memory having entries each storing an operand address and operand data corresponding to the operand address in its entry. The data processor executes an instruction that makes entries in both of said instruction cache memory and said operand cache memory ineffective.
摘要翻译：形成在LSI芯片上的数据处理器具有指令地址发生器，指令高速缓冲存储器，其具有各自存储指令地址的条目和与该指令地址对应的指令，指令译码器从对应于指令地址的所述高速缓冲存储器解码指令所述指令地址生成器，响应于所述指令解码器的输出信号产生操作数地址的操作数地址生成器和具有条目的操作数高速缓存存储器，每个存储操作数地址和对应于其操作数地址的操作数数据。数据处理器执行使得在所述指令高速缓冲存储器和所述操作数高速缓冲存储器两者中的条目无效的指令。

3. 发明授权

US5202969A Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively 失效
标题翻译：单片缓存缓冲器，用于基于位和位串的指示，有选择地写入回写和独占地将数据块部分写入主存储器
公开(公告)号：US5202969A
公开(公告)日：1993-04-13
申请号：US871906
申请日：1992-04-21
申请人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
发明人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G06F12/0804 , G11C11/4096
摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
摘要翻译：在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。在缓冲寄存器和数据存储器之间连接一个选择器。该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。这种布置为高速缓冲存储器提供部分写入功能。

4. 发明授权

US4937738A Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction 失效
标题翻译：数据处理系统，其基于指令的位信息选择性地绕过高速缓冲存储器取得信息
公开(公告)号：US4937738A
公开(公告)日：1990-06-26
申请号：US768572
申请日：1985-08-23
申请人： Kunio Uchiyama , Atsushi Hasegawa , Takeshi Aimoto , Tadahiko Nishimukai
发明人： Kunio Uchiyama , Atsushi Hasegawa , Takeshi Aimoto , Tadahiko Nishimukai
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： A cache memory contained in a processor features a high efficiency in spite of its small capacity.In the cache memory control circuit, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory.By assigning the particular region for the data that is to be used repeatedly, it is possible to provide a cache memory having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.
摘要翻译：包含在处理器中的高速缓冲存储器具有高效率，尽管其容量小。在高速缓冲存储器控制电路中，检测处理器的访问操作是否针对存储器的特定区域，并且当数据要被从特定区域读出或被写入时，数据被复制到高速缓冲存储器上，并且当数据要从其他区域读出时，立即执行存储器的操作而不等待缓存存储器的引用。通过为要重复使用的数据分配特定区域，可以提供尽管容量小的高效率的高速缓冲存储器。这种数据的代表性例子是堆栈中的数据。

5. 发明授权

US5146573A Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register 失效
标题翻译：具有部分写入电路的单芯片缓存，用于在存储器和缓冲寄存器之间传输预选的数据部分
公开(公告)号：US5146573A
公开(公告)日：1992-09-08
申请号：US426781
申请日：1989-10-25
申请人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
发明人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G11C11/4096 , G06F12/0804
摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
摘要翻译：在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。在缓冲寄存器和数据存储器之间连接一个选择器。该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。这种布置为高速缓冲存储器提供部分写入功能。

6. 发明授权

US4989140A Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit 失效
标题翻译：单芯片流水线数据处理器采用指令和操作数缓存存储器，用于并行操作指令控制和执行单元
公开(公告)号：US4989140A
公开(公告)日：1991-01-29
申请号：US323125
申请日：1989-03-13
申请人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Ikuya Kawasaki , Makoto Hanawa
发明人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Ikuya Kawasaki , Makoto Hanawa
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instruction read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output the instruction to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译：用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，该指令控制单元具有从主存储器读出的第一相关存储器存储指令，以及指令控制器，当该指令为指令时，从第一关联存储器读出指令存在于第一关联存储器中，并且当指令不存在于第一关联存储器中时，指令控制单元产生要执行的指令的输出。指令执行单元具有第二关联存储器，其存储从主存储器读出的操作数数据，以及指令执行器，当所述操作数数据存在于所述第二关联存储器中时，通过使用从所述第二关联存储器读出的操作数据来执行所述指令; 当操作数数据不存在于第二关联存储器中时，从主存储器。

7. 发明授权

US4803616A Buffer memory 失效
标题翻译：缓冲存储器
公开(公告)号：US4803616A
公开(公告)日：1989-02-07
申请号：US781512
申请日：1985-09-30
申请人： Kunio Uchiyama , Tadahiko Nishimukai , Atsushi Hasegawa
发明人： Kunio Uchiyama , Tadahiko Nishimukai , Atsushi Hasegawa
IPC分类号： G06F12/08 , G06F13/00 , G06F12/06
CPC分类号： G06F12/0895
摘要： In a buffer memory, a validity flag to be added to each data portion is stored in a tag array or address section at a location corresponding to each data portion. After determining whether each validity flag is to be used as a search object, based upon the data portion to be accessed during searching the tag array and an access mode, the address and its validity flag are simultaneously searched. The logical sum of each output of the search result on a word coincidence line becomes a hit judgement signal.
摘要翻译：在缓冲存储器中，要添加到每个数据部分的有效性标志被存储在与每个数据部分相对应的位置处的标签阵列或地址部分中。在确定是否将每个有效性标志用作搜索对象之后，基于在搜索标签阵列期间要访问的数据部分和访问模式，同时搜索地址及其有效性标志。字符符号线上的搜索结果的每个输出的逻辑和成为命中判断信号。

8. 发明授权

US06272596B1 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US06272596B1
公开(公告)日：2001-08-07
申请号：US09396414
申请日：1999-09-15
申请人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Ikuya Kawasaki , Makoto Hanawa
发明人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Ikuya Kawasaki , Makoto Hanawa
IPC分类号： G06F1202
CPC分类号： G06F9/30047 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0848 , G06F12/0891
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executor executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译：用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。控制器还具有要执行的指令的输出。指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。

9. 发明授权

US4912635A System for reexecuting branch instruction without fetching by storing target instruction control information 失效
标题翻译：用于通过存储目标指令控制信息重新执行分支指令而不进行提取的系统
公开(公告)号：US4912635A
公开(公告)日：1990-03-27
申请号：US151276
申请日：1988-02-01
申请人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Yoshifumi Takamoto
发明人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Yoshifumi Takamoto
IPC分类号： G06F9/38
CPC分类号： G06F9/3846
摘要： The present invention relates to a pipeline data processing apparatus wherein an instruction is fetched from a main storage, the instruction is decoded to generate control information for executing the instruction, and the control information is transferred to an instruction execute circuit. The target address of a branch instruction is stored in the index field of an associative memory, and control information obtained by decoding a target instruction of branch corresponding to the branch instruction is stored in the data field of the associative memory beforehand. When executing the branch instruction, the associative memory is accessed with the target address, and the control information of the corresponding entry is read out and is transferred to the instruction execute circuit, whereupon the instruction execute circuit starts executing the target instruction of branch instruction in succeession to the execution of the branch instruction.
摘要翻译：本发明涉及一种流水线数据处理装置，其中从主存储器取出指令，解码指令以产生用于执行指令的控制信息，并将控制信息传送到指令执行电路。分支指令的目标地址被存储在关联存储器的索引字段中，并且通过解码与分支指令相对应的分支的目标指令获得的控制信息被预先存储在关联存储器的数据字段中。当执行分支指令时，利用目标地址访问关联存储器，读出对应条目的控制信息并将其传送到指令执行电路，由此指令执行电路开始执行分支指令的目标指令成功执行分支指令。

10. 发明授权

US4797816A Virtual memory supported processor having restoration circuit for register recovering 失效
标题翻译：虚拟内存支持的处理器具有用于寄存器恢复的恢复电路
公开(公告)号：US4797816A
公开(公告)日：1989-01-10
申请号：US822231
申请日：1986-01-24
申请人： Kunio Uchiyama , Tadahiko Nishimukai
发明人： Kunio Uchiyama , Tadahiko Nishimukai
IPC分类号： G06F12/10 , G06F9/38 , G06F9/46 , G06F12/08
CPC分类号： G06F9/3863 , G06F9/461
摘要： A register recovering system for a data processor having a group of general-purpose registers includes a saving register for saving the content of the general-purpose register; a control register for storing discrimination information for the general-purpose register; a setting unit for setting the discrimination information at the control register, based on instruction information of a machine code to be processed by the data processor; and a setting unit for setting the content of the saving register to the general-purpose register in accordance with the discrimination information stored in the control register.
摘要翻译：一种用于具有一组通用寄存器的数据处理器的寄存器恢复系统，包括用于保存通用寄存器的内容的保存寄存器; 用于存储用于通用寄存器的识别信息的控制寄存器; 基于要由数据处理器处理的机器代码的指令信息，设置单元，用于在控制寄存器中设置鉴别信息; 以及设置单元，用于根据存储在控制寄存器中的识别信息将保存寄存器的内容设置到通用寄存器。

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