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1. 发明授权

US4716522A Microcomputer system with buffer in peripheral storage control 失效
标题翻译：微机系统具有缓冲区外设存储控制
公开(公告)号：US4716522A
公开(公告)日：1987-12-29
申请号：US473861
申请日：1983-03-10
申请人： Tsuneo Funabashi , Kazuhiko Iwasaki , Hideo Nakamura
发明人： Tsuneo Funabashi , Kazuhiko Iwasaki , Hideo Nakamura
IPC分类号： G06F3/06 , G06F13/00 , G06F13/28
CPC分类号： G06F3/0601 , G06F13/28 , G06F2003/0691
摘要： A microcomputer system has a peripheral storage control equipped with both a circuit which is responsive to a transfer command received from an MPU to set in a counter a transfer start address, which is designated subsequent to that command. The counter to supply an address for a buffer to control transfer of data from the output of the buffer to a common bus connected between the MPU and a RAM. A circuit is provided for controlling the aforementioned counter to count up in response to a transfer acknowledge signal which is subsequently received from a direct memory access control. In order that the data in the buffer may not be transferred to the RAM but may be rewritten, the peripheral storage control is further equipped with both a circuit for setting a rewrite address also received from the MPU in the counter, which is operative to identify the address of the selected buffer, in association with a rewrite command received from the MPU, and a circuit is also provided for applying the rewrite signal to the buffer each time the rewrite data is received after the setting operation from the MPU.
摘要翻译：微型计算机系统具有外围存储控制，该外围存储控制装置具有响应于从MPU接收到的传送命令的电路，在计数器中设置在该命令之后指定的传送起始地址。该计数器为缓冲器提供地址，以控制从缓冲器的输出到连接在MPU和RAM之间的公共总线的数据传输。提供电路，用于响应于随后从直接存储器访问控制接收的传送确认信号来控制上述计数器进行计数。为了缓冲器中的数据可能不被传送到RAM但是可以被重写，外围存储控制还配备有用于设置也从计数器中的MPU接收的重写地址的电路，其可操作地识别还提供与从MPU接收的重写命令相关联的所选择的缓冲器的地址和电路，用于在每次在来自MPU的设置操作之后接收到重写数据时，将重写信号施加到缓冲器。

2. 发明授权

US4387294A Shift register-latch circuit driven by clocks with half cycle phase deviation and usable with a serial alu 失效
标题翻译：由具有半周期相位偏差的时钟驱动的移位寄存器锁存电路，可用于串行alu
公开(公告)号：US4387294A
公开(公告)日：1983-06-07
申请号：US147078
申请日：1980-05-07
申请人： Hideo Nakamura , Tsuneo Funabashi
发明人： Hideo Nakamura , Tsuneo Funabashi
IPC分类号： G11C19/18 , G11C19/28 , G06F7/48
CPC分类号： G11C19/184 , G11C19/28
摘要： In a multiple stage data transfer circuit, suitable for transferring a plurality of bits to or from a bit processor or 1-bit arithmetic logic unit, each bit stage includes a shift register portion and a latch portion. Each shift register(S/R) portion is constructed of a series circuit consisting of a static (input) inverter, a switching element, and a dynamic (output) inverter. Each latch portion is constructed of a closed loop consisting of a static inverter, a switching element, and a dynamic inverter. Each bit stage also includes a data transfer switch element, which may be activated through an externally connected control line. The data transfer switch is coupled beween the data output terminal of the S/R switch and the data output terminal of the latch switch. The S/R and latch portion switches are activated by two different clocks, with a phase deviation therebetween of one-half cycle. When the S/R switch and data transfer switch are both "ON", data may flow from the S/R's input inverter to the latch. When the latch switch and the data transfer switch are both "ON", data may flow from the latch to the S/R's output inverter.
摘要翻译：在多级数据传输电路中，适用于向位处理器或1位运算逻辑单元传送多个位，每个位级包括移位寄存器部分和锁存部分。每个移位寄存器（S / R）部分由由静态（输入）反相器，开关元件和动态（输出）反相器组成的串联电路构成。每个闩锁部分由包括静态逆变器，开关元件和动态逆变器的闭环构成。每个位级还包括数据传输开关元件，其可以通过外部连接的控制线被激活。数据传输开关耦合在S / R开关的数据输出端和锁存开关的数据输出端之间。 S / R和锁存部分开关由两个不同的时钟激活，其间的相位偏差为两个周期。当S / R开关和数据传输开关均为“ON”时，数据可能会从S / R的输入变频器流向锁存器。当锁存开关和数据传输开关均为“ON”时，数据可能会从锁存器流向S / R的输出变频器。

3. 发明授权

US5019962A Direct memory access controller for a multi-microcomputer system 失效
标题翻译：用于多微机系统的直接存储器存取控制器
公开(公告)号：US5019962A
公开(公告)日：1991-05-28
申请号：US144523
申请日：1988-01-15
申请人： Tsuneo Funabashi , Kaoru Sakoshita , Hiroshi Yonezawa
发明人： Tsuneo Funabashi , Kaoru Sakoshita , Hiroshi Yonezawa
IPC分类号： G06F15/167 , G06F13/28 , G06F15/17
CPC分类号： G06F13/285 , G06F15/17
摘要： A multi-microcomputer system comprising a first microcomputer system, a second microcomputer system, and a direct memory access controller which has a function of controlling a data transfer operation that is executed between the first microcomputer system and the second microcomputer system.

4. 发明授权

US4773002A Microprogram controller in which instruction following conditional branch instruction is selectively converted to a NOP instruction 失效
标题翻译：微程序控制器，其中指令跟随条件分支指令被选择性地转换为NOP指令
公开(公告)号：US4773002A
公开(公告)日：1988-09-20
申请号：US865388
申请日：1986-05-21
申请人： Kazuhiko Iwasaki , Noboru Yamaguchi , Tsuneo Funabashi , Junichi Tatezaki , Takanori Shimura
发明人： Kazuhiko Iwasaki , Noboru Yamaguchi , Tsuneo Funabashi , Junichi Tatezaki , Takanori Shimura
IPC分类号： G06F9/28 , G06F9/22 , G06F9/26 , G06F9/32 , G06F9/38
CPC分类号： G06F9/264
摘要： In a microprogram controller by pipeline control which includes a memory for storing a microprogram and a program counter for representing the address of the memory, a microprogram controller includes means for judging whether or not a branch condition of a branch microinstruction is satisfied and means for converting the microinstruction fetched from the memory to a NOP (No Operation) microinstruction from the output of the next step of the memory till the outputs after a plurality of steps by the affirmation output of the judging means. When the affirmation output is obtained from the judging means, part of the memory output is loaded into the program counter and when the negation output is obtained, a value as the sum of a current value plus 1 is loaded into the program counter.
摘要翻译：在通过流水线控制的微程序控制器中，包括用于存储微程序的存储器和用于表示存储器的地址的程序计数器，微程序控制器包括用于判断分支微指令的分支条件是否满足的装置和用于转换的装置通过判断装置的肯定输出，从存储器的下一个步骤的输出，从存储器中取出的微指令到NOP（无操作）微指令，直到多个步骤之后的输出。当从判断装置获得确认输出时，存储器输出的一部分被加载到程序计数器中，并且当获得否定输出时，将作为当前值加1的和的值加载到程序计数器中。

5. 发明授权

US4677623A Decoding method and apparatus for cyclic codes 失效
标题翻译：用于循环码的解码方法和装置
公开(公告)号：US4677623A
公开(公告)日：1987-06-30
申请号：US669423
申请日：1984-11-08
申请人： Kazuhiko Iwasaki , Junichi Tatezaki , Tsuneo Funabashi
发明人： Kazuhiko Iwasaki , Junichi Tatezaki , Tsuneo Funabashi
IPC分类号： H03M1/00 , H03M13/17 , G06F11/10
CPC分类号： H03M13/17
摘要： In an apparatus for decoding cyclic codes generated by a generator polynomial ##EQU1## (where P.sub.i (x) is a m.sub.i -order irreducible polynomial) including 0-th to l-th feedback shift registers corresponding to the terms (x.sup.c +1) and P.sub.i (x), a coincidence circuit for detecting coincidence of a predetermined number of low order bits of said 0-th to l-th feedback shift registers and all-zero conditions of a high order bits, the predetermined number being a minimum one of numbers of bits (c, m.sub.1, m.sub.2, . . . m.sub.l) of the feedback shift register, the 0-th feedback shift register having an output terminal thereof connected to an input terminal thereof, and the 1st to l-th feedback shift registers each having an output terminal thereof connected to an input terminal thereof and having exclusive OR gates inserted between stages determined by the associated simple polynomial, exclusive OR gates each receiving the output of the associated feedback shift register as one input thereto; a method for decoding the cyclic code for correcting a burst error by shifting the 0-th to l-th feedback shift registers until the coincidence circuit detects the coincidence, comprising the steps of; shifting at least one of said 0-th to l-th feedback shift registers a predetermined number of times; and simultaneously shifting the 0-th to l-th feedback shift registers after the predetermined number of shifting until the coincidence circuit detects the coincidence.
摘要翻译：在用于解码由生成多项式（其中Pi（x）是mi阶不可约数多项式）生成的循环码的装置，包括对应于项（xc + 1）的第0至第1反馈移位寄存器和 Pi（x），用于检测所述第0至第1反馈移位寄存器的预定数量的低位比特和高位比特的全零条件的符合电路，所述预定数是反馈移位寄存器的位数（c，m1，m2，...），第0反馈移位寄存器，其输出端连接到其输入端，第1至第1反馈移位寄存器每个具有连接到其输入端的输出端，并且具有插入在由相关联的简单多项式确定的级之间的异或门，每个异或门接收相关联的反馈移位寄存器的输出作为其一个输入; 一种用于通过移位第0到第1反馈移位寄存器来纠正突发错误的循环码的解码方法，直到符合电路检测到重合为止，包括以下步骤：将所述第0到第1反馈移位寄存器中的至少一个移位预定次数; 并且在预定的移位数之后同时移动第0到第1反馈移位寄存器，直到符合电路检测到一致。

6. 发明授权

US4674037A Data processing system with an enhanced communication control system 失效
标题翻译：具有增强型通信控制系统的数据处理系统
公开(公告)号：US4674037A
公开(公告)日：1987-06-16
申请号：US690609
申请日：1985-01-11
申请人： Tsuneo Funabashi , Kazuhiko Iwasaki , Noboru Yamaguchi , Takanori Shimura , Junichi Tatezaki
发明人： Tsuneo Funabashi , Kazuhiko Iwasaki , Noboru Yamaguchi , Takanori Shimura , Junichi Tatezaki
IPC分类号： H04L29/02 , G06F13/00 , G06F15/16 , G06F15/167 , G06F15/177
CPC分类号： G06F15/167
摘要： A data buffer is connected to the first and second processor and the first processor sends a start signal to the second processor, which responds to the start signal by reading data from a data source, such as an input/output device, and then writes the read out data into the data buffer. After conclusion of the writing operation, the second processor sends an end signal to the first processor which is admitted to start sending data stored in the buffer to a host processor after receipt of the start signal. The start signal and the end signal are provided to the second processor and the first processor respectively, after passing through a synchronizing circuit.
摘要翻译：数据缓冲器连接到第一处理器和第二处理器，第一处理器向第二处理器发送起始信号，第二处理器通过从数据源（例如输入/输出设备）读取数据来响应起始信号，然后写入读出数据到数据缓冲区。在写入操作结束之后，第二处理器向接收到开始信号的主处理器发送结束信号给第一处理器，该第一处理器被允许开始向主处理器发送存储在缓冲器中的数据。开始信号和结束信号分别在通过同步电路之后提供给第二处理器和第一处理器。

7. 发明授权

US5222227A Direct memory access controller for a multi-microcomputer system 失效
标题翻译：用于多微机系统的直接存储器存取控制器
公开(公告)号：US5222227A
公开(公告)日：1993-06-22
申请号：US855456
申请日：1992-03-19
申请人： Tsuneo Funabashi , Kaoru Sakoshita , Hiroshi Yonezawa
发明人： Tsuneo Funabashi , Kaoru Sakoshita , Hiroshi Yonezawa
IPC分类号： G06F13/28 , G06F15/17
CPC分类号： G06F15/17 , G06F13/285
摘要： A multi-microcomputer system comprising a first microcomputer system, a second microcomputer system, and a direct memory access controller which has a function of controlling a data transfer operation that is executed between the first microcomputer system and the second microcomputer system.
摘要翻译：一种包括第一微型计算机系统，第二微型计算机系统和具有控制在第一微机系统和第二微机系统之间执行的数据传送操作的功能的直接存储器存取控制器的多微机系统。

8. 发明授权

US5047920A Hierarchal system for reducing memory access time to plural equal sized memories by simultaneously addressing and accessing memory 失效
标题翻译：分层系统，用于通过同时寻址和访问存储器来将存储器访问时间减少到多个等大小的存储器
公开(公告)号：US5047920A
公开(公告)日：1991-09-10
申请号：US346242
申请日：1989-05-02
申请人： Tsuneo Funabashi
发明人： Tsuneo Funabashi
IPC分类号： G06F12/08
CPC分类号： G06F12/0884
摘要： When a CPU outputs an address for read-out from a memory, access to a cache memory is immediately started by use of its address signal, and in the mean time a cache controller determines whether or not the data required by the CPU exists in the cache memory and, if so, generates a selection signal for outputting only the data read out from a desired bank of the cache memory to a data bus. Acccordingly, the time necessary for address comparison in the cache controller is not added to the access cycle time of the cache memory so that the overall access time can be shortened and the through-put of the system can be improved.
摘要翻译：当CPU从存储器输出读出地址时，通过使用其地址信号立即开始对高速缓冲存储器的访问，同时高速缓存控制器确定CPU中所需的数据是否存在于高速缓冲存储器，如果是，则产生选择信号，用于仅将从期望的高速缓存存储体读出的数据输出到数据总线。因此，缓存控制器中的地址比较所需的时间不被添加到高速缓冲存储器的访问周期时间，从而可以缩短总访问时间并且可以提高系统的占用。

9. 发明授权

US4894768A Data processing system with coprocessor 失效
标题翻译：数据处理系统与协处理器
公开(公告)号：US4894768A
公开(公告)日：1990-01-16
申请号：US21007
申请日：1987-03-02
申请人： Kazuhiko Iwasaki , Tsuneo Funabashi , Ikuya Kawasaki , Hideo Inayoshi , Atsushi Hasegawa , Takao Yaginuma , Eiki Kondoh
发明人： Kazuhiko Iwasaki , Tsuneo Funabashi , Ikuya Kawasaki , Hideo Inayoshi , Atsushi Hasegawa , Takao Yaginuma , Eiki Kondoh
IPC分类号： G06F15/16 , G06F9/38 , G06F15/167
CPC分类号： G06F15/167 , G06F9/3877
摘要： When a microprocessor fetches an instruction to be processed by a coprocessor, it sends to the coprocessor a command corresponding to the instruction while informing the coprocessor that the bus cycle is in the mode of transfer of the instruction to the coprocessor. In transferring an operand from the memory to the coprocessor, the microprocessor asserts, in addition to a usual memory read signal, a signal (CYCYCL) indicative of validity of the coprocessor and instructs the coprocessor to fetch data to thereby complete the operand transfer from memory to coprocessor within one bus cycle. In transferring data from the coprocessor to the memory, the microprocessor asserts, in addition to a usual memory write signal, the CYCYCL signal and instructs the coprocessor to deliver the data to thereby complete the data transfer from memory to coprocessor within one bus cycle. Thus, the signal transfer between memory and coprocessor can be completed within one bus cycle without resort to the provision of duplicate hardware in the coprocessor.
摘要翻译：当微处理器提取要由协处理器处理的指令时，它向协处理器发送与指令相对应的命令，同时通知协处理器总线周期处于向协处理器传送指令的模式。在将操作数从存储器传送到协处理器时，除了通常的存储器读取信号之外，微处理器还断言指示协处理器的有效性的信号（＆upbar＆C /），并且指示协处理器提取数据从而完成操作数传送从一个总线周期内的存储器到协处理器。在将数据从协处理器传输到存储器时，微处理器除了通常的存储器写入信号之外，还断言＆upbar＆C /信号并指示协处理器传送数据，从而完成在一个总线周期内从存储器到协处理器的数据传输。因此，存储器和协处理器之间的信号传输可以在一个总线周期内完成，而不需要在协处理器中提供重复的硬件。

10. 发明授权

US4319226A Signal converter utilizing two clock signals 失效
标题翻译：信号转换器利用两个时钟信号
公开(公告)号：US4319226A
公开(公告)日：1982-03-09
申请号：US26768
申请日：1979-04-03
申请人： Hideo Nakamura , Katsuaki Takagi , Tsuneo Funabashi
发明人： Hideo Nakamura , Katsuaki Takagi , Tsuneo Funabashi
IPC分类号： G01R29/02 , H03M1/00 , H03M1/50 , H03M1/54 , G06F7/38 , H03K13/02
CPC分类号： H03M1/50
摘要： A signal converter includes a generator for generating first and second clock signals having recurrence periods equal to each other and phases different from each other, an input for receiving as a signal to be converted a signal which has signal levels not lower than a predetermined level during an arbitrary period of time, a counter for counting the first clock signals from the generator in a period of time corresponding to the signal period of time, and an output arrangement. The output arrangement provides for delivering either of two signals in dependence on which of time intervals determined by the first and second clock signals an end of said signal period of time lies in, whereby signals of the counter and the output arrangement are used as a converted signal.
摘要翻译：信号转换器包括：发生器，用于产生具有彼此相等且相位不同的重复周期的第一和第二时钟信号;输入端，用于接收作为转换信号的信号，该信号具有不低于预定电平的信号电平任意的时间段，用于在对应于信号时间段的时间段内对来自发生器的第一时钟信号进行计数的计数器，以及输出装置。输出装置提供了根据由第一和第二时钟信号确定的时间间隔中的任何一个输出任一个信号，所述信号时间周期的结束位于其中，由此计数器和输出装置的信号被用作转换的信号。

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