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1. 发明授权

US08169080B2 Semiconductor device and method of manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08169080B2
公开(公告)日：2012-05-01
申请号：US12940419
申请日：2010-11-05
申请人： Noboru Morimoto , Masahiko Fujisawa , Daisuke Kodama
发明人： Noboru Morimoto , Masahiko Fujisawa , Daisuke Kodama
IPC分类号： H01L23/48
CPC分类号： H01L21/768 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.
摘要翻译：在半导体基板上形成电路的区域和切割区域之间设置有密封环。密封环具有其横截面形状为T形的密封层被层叠的部分和横截面形状为矩形的密封层的部分。

2. 发明申请

US20070090447A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070090447A1
公开(公告)日：2007-04-26
申请号：US11551042
申请日：2006-10-19
申请人： Noboru MORIMOTO , Masahiko Fujisawa , Daisuke Kodama
发明人： Noboru MORIMOTO , Masahiko Fujisawa , Daisuke Kodama
IPC分类号： H01L29/788
CPC分类号： H01L21/768 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.
摘要翻译：在半导体基板上形成电路的区域和切割区域之间设置有密封环。密封环具有其横截面形状为T形的密封层被层叠的部分和横截面形状为矩形的密封层的部分。

3. 发明授权

US07884011B2 Semiconductor device and method of manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07884011B2
公开(公告)日：2011-02-08
申请号：US12721048
申请日：2010-03-10
申请人： Noboru Morimoto , Masahiko Fujisawa , Daisuke Kodama
发明人： Noboru Morimoto , Masahiko Fujisawa , Daisuke Kodama
IPC分类号： H01L21/4763
CPC分类号： H01L21/768 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.
摘要翻译：在半导体基板上形成电路的区域和切割区域之间设置有密封环。密封环具有其横截面形状为T形的密封层被层叠的部分和横截面形状为矩形的密封层的部分。

4. 发明申请

US20110101530A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110101530A1
公开(公告)日：2011-05-05
申请号：US12940419
申请日：2010-11-05
申请人： Noboru MORIMOTO , Masahiko Fujisawa , Daisuke Kodama
发明人： Noboru MORIMOTO , Masahiko Fujisawa , Daisuke Kodama
IPC分类号： H01L23/532
CPC分类号： H01L21/768 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.
摘要翻译：在半导体基板上形成电路的区域和切割区域之间设置有密封环。密封环具有其横截面形状为T形的密封层被层叠的部分和横截面形状为矩形的密封层的部分。

5. 发明申请

US20100167525A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100167525A1
公开(公告)日：2010-07-01
申请号：US12721048
申请日：2010-03-10
申请人： Noboru Morimoto , Masahiko Fujisawa , Daisuke Kodama
发明人： Noboru Morimoto , Masahiko Fujisawa , Daisuke Kodama
IPC分类号： H01L21/768
CPC分类号： H01L21/768 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.
摘要翻译：在半导体基板上形成电路的区域和切割区域之间设置有密封环。密封环具有其横截面形状为T形的密封层被层叠的部分和横截面形状为矩形的密封层的部分。

6. 发明授权

US07714413B2 Semiconductor device and method of manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07714413B2
公开(公告)日：2010-05-11
申请号：US11551042
申请日：2006-10-19
申请人： Noboru Morimoto , Masahiko Fujisawa , Daisuke Kodama
发明人： Noboru Morimoto , Masahiko Fujisawa , Daisuke Kodama
IPC分类号： H01L23/544
CPC分类号： H01L21/768 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.
摘要翻译：在半导体基板上形成电路的区域和切割区域之间设置有密封环。密封环具有其横截面形状为T形的密封层被层叠的部分和横截面形状为矩形的密封层的部分。

7. 发明授权

US06780769B2 Method of manufacturing structure for connecting interconnect lines including metal layer with thickness larger than thickness of metallic compound layer 有权
标题翻译：制造包括厚度大于金属化合物层厚度的金属层的互连线的结构的制造方法
公开(公告)号：US06780769B2
公开(公告)日：2004-08-24
申请号：US10464502
申请日：2003-06-19
申请人： Masahiko Fujisawa , Akihiko Ohsaki , Noboru Morimoto
发明人： Masahiko Fujisawa , Akihiko Ohsaki , Noboru Morimoto
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12). In view of this, in order to improve the adhesion especially between the second copper interconnect line (6) at the region for filling the contact hole (12) and the second conductive barrier layer (20), the metal layer (9) is provided.
摘要翻译：从第一铜互连线（2）和层间绝缘膜（5）的侧面观察时，依次层叠金属层（7），金属化合物层（8）和金属层（9），构成第二导电阻挡层（20）。作为金属层（7）和（9）的材料，可以使用原子量高于诸如钨（W）或钽（Ta）的铜的元素。第二铜互连线（6）通过第二导电阻挡层（20）在接触孔（12）处导电地连接到第一铜互连线（2）。由于在填充接触孔（12）的区域处，用于填充沟槽（11）的区域处的第二铜互连线（6）的体积与第二铜互连线（6）的体积的比率增加，要集中在接触孔（12）处的拉伸应力变大。结果，在接触孔（12）中容易产生空隙。鉴于此，为了改善在用于填充接触孔（12）的区域和第二导电阻挡层（20）之间的第二铜互连线（6）之间的粘合性，提供了金属层（9）。

8. 发明授权

US06664641B2 Wiring structure for an integrated circuit 失效
标题翻译：集成电路的接线结构
公开(公告)号：US06664641B2
公开(公告)日：2003-12-16
申请号：US10261653
申请日：2002-10-02
申请人： Akihiko Ohsaki , Masahiko Fujisawa , Noboru Morimoto
发明人： Akihiko Ohsaki , Masahiko Fujisawa , Noboru Morimoto
IPC分类号： H01L2710
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A wire width and a wiring space of each of signal wires 1 and ground/power wires 2 are determined to be a wire width W1 (the minimum wire width) and a wiring space S1, respectively. A wire width and a wiring space of the via-hole neighboring region 1a or 2a are determined to be a wire width W2 (>W1) and a wiring space S2 (
摘要翻译：信号线1和接地/电力线2的线宽和布线空间分别被确定为线宽W1（最小线宽）和布线空间S1。通孔相邻区域1a或2a的线宽度和布线空间分别被确定为线宽W2（> W1）和布线空间S2（ = 0.6}。此外，信号线1和接地/电力线2具有与宽度比（T1 / W1）等于或高于2的线材厚度T1相同的线材厚度。

9. 发明授权

US06624516B2 Structure for connecting interconnect lines with interposed layer including metal layers and metallic compound layer 有权
标题翻译：用于连接具有包括金属层和金属化合物层的插入层的互连线的结构
公开(公告)号：US06624516B2
公开(公告)日：2003-09-23
申请号：US09978005
申请日：2001-10-17
申请人： Masahiko Fujisawa , Akihiko Ohsaki , Noboru Morimoto
发明人： Masahiko Fujisawa , Akihiko Ohsaki , Noboru Morimoto
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12). In view of this, in order to improve the adhesion especially between the second copper interconnect line (6) at the region for filling the contact hole (12) and the second conductive barrier layer (20), the metal layer (9) is provided.
摘要翻译：从第一铜互连线（2）和层间绝缘膜（5）的侧面观察时，依次层叠金属层（7），金属化合物层（8）和金属层（9），构成第二导电阻挡层（20）。作为金属层（7）和（9）的材料，可以使用原子量高于诸如钨（W）或钽（Ta）的铜的元素。第二铜互连线（6）通过第二导电阻挡层（20）在接触孔（12）处导电地连接到第一铜互连线（2）。由于在填充接触孔（12）的区域处，用于填充沟槽（11）的区域处的第二铜互连线（6）的体积与第二铜互连线（6）的体积的比率增加，要集中在接触孔（12）处的拉伸应力变大。结果，在接触孔（12）中容易产生空隙。鉴于此，为了改善在用于填充接触孔（12）的区域和第二导电阻挡层（20）之间的第二铜互连线（6）之间的粘合性，提供了金属层（9）。

10. 发明授权

US5565708A Semiconductor device comprising composite barrier layer 失效
标题翻译：包括复合阻挡层的半导体器件
公开(公告)号：US5565708A
公开(公告)日：1996-10-15
申请号：US440808
申请日：1995-05-15
申请人： Akihiko Ohsaki , Sumio Yamaguchi , Atsushi Ishii , Kazuyoshi Maekawa , Masahiko Fujisawa
发明人： Akihiko Ohsaki , Sumio Yamaguchi , Atsushi Ishii , Kazuyoshi Maekawa , Masahiko Fujisawa
IPC分类号： H01L21/28 , C23C14/06 , C23C14/18 , C23C14/58 , H01L21/203 , H01L21/205 , H01L21/285 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/532 , H01L23/48 , H01L29/46 , H01L29/54 , H01L29/62
CPC分类号： C23C14/5806 , C23C14/0641 , C23C14/185 , H01L21/28518 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76856 , H01L23/485 , H01L23/53257 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor device comprising conductors electrically connected through a contact hole interlayer insulation layer with a trilayer barrier layer comprising a titanium silicide layer, titanium silicide layer formed on the titanium silicide by collimation sputtering, and a thermally nitrided titanium formed on the titanium nitride layer. The use of a trilayer barrier layer enables through the capacity of the collimation sputtering apparatus to be increased, prevents particles from occurring, and formation of a low resistance electrical connection between conductors, in addition to preventing diffusion from the titanium nitride layer and the second titanium layer to the thermally nitrided titanium layer, and between conductors.
摘要翻译：一种半导体器件，包括通过接触孔层间绝缘层与通过准直溅射形成在硅化钛上的钛硅化物层，硅化钛层和形成在氮化钛层上的热氮化钛的三层势垒层电连接的导体。除了防止从氮化钛层和第二钛的扩散之外，使用三层阻挡层能够增加准直溅射装置的容量，防止颗粒发生，以及形成导体之间的低电阻电连接层到热氮化钛层和导体之间。

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