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1. 发明授权

US09405707B2 Secure replay protected storage 有权
标题翻译：安全重放保护存储
公开(公告)号：US09405707B2
公开(公告)日：2016-08-02
申请号：US13997896
申请日：2011-12-20
申请人： Nitin V. Sarangdhar , William A. Stevens, Jr. , John J. Vranich
发明人： Nitin V. Sarangdhar , William A. Stevens, Jr. , John J. Vranich
IPC分类号： G06F11/30 , G06F12/14 , G06F13/14
CPC分类号： G06F12/1408 , G06F13/14 , G06F21/44 , G06F21/79 , G06F2212/1052
摘要： Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such that it may be protected against user attacks—e.g., replacing the SPI flash memory device or a man-in-the-middle (MITM) attack to modify the SPI flash memory contents on the fly. In the prior art, monotonic counters cannot be stored in SPI flash memory devices because said devices do not provide replay protection for the counters. A user may also remove the flash memory device and reprogram it. Host platforms alone cannot protect against such hardware attacks.Embodiments of the invention enable secure standard storage flash memory devices such as SPI flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and HMAC key logic to create secure execution environments for various components.
摘要翻译：本发明的实施例在闪存设备（例如，串行外围设备接口（SPI）闪存设备）中创建底层基础设施，使得其可以被保护免受用户攻击 - 例如，替换SPI闪存设备或管理员 - 中间（MITM）攻击，即时修改SPI闪存内容。在现有技术中，单调计数器不能存储在SPI闪存设备中，因为所述设备不为计数器提供重放保护。用户还可以移除闪存设备并对其进行重新编程。仅主机平台无法防范此类硬件攻击。本发明的实施例使得诸如SPI闪存设备之类的安全标准存储闪存设备能够实现用于安全存储的数据的重放保护。本发明的实施例利用闪存控制器，闪存设备，唯一设备密钥和HMAC密钥逻辑来为各种组件创建安全的执行环境。

2. 发明申请

US20130159727A1 SECURE REPLAY PROTECTED STORAGE 有权
标题翻译：安全重置保护存储
公开(公告)号：US20130159727A1
公开(公告)日：2013-06-20
申请号：US13631556
申请日：2012-09-28
申请人： Nitin V. Sarangdhar , William A. Stevens, JR. , John J. Vranich
发明人： Nitin V. Sarangdhar , William A. Stevens, JR. , John J. Vranich
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F21/445 , G06F21/79
摘要： Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such that it may be protected against user attacks—e.g., replacing the SPI flash memory device or a man-in-the-middle (MITM) attack to modify the SPI flash memory contents on the fly. In the prior art, monotonic counters cannot be stored in SPI flash memory devices because said devices do not provide replay protection for the counters. A user may also remove the flash memory device and reprogram it. Host platforms alone cannot protect against such hardware attacks.Embodiments of the invention enable secure standard storage flash memory devices such as SPI flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and HMAC key logic to create secure execution environments for various components.
摘要翻译：本发明的实施例在闪存设备（例如，串行外围设备接口（SPI）闪存设备）中创建底层基础设施，使得其可以被保护免受用户攻击 - 例如，替换SPI闪存设备或管理员 - 中间（MITM）攻击，即时修改SPI闪存内容。在现有技术中，单调计数器不能存储在SPI闪存设备中，因为所述设备不为计数器提供重放保护。用户还可以移除闪存设备并对其进行重新编程。仅主机平台无法防范此类硬件攻击。本发明的实施例使得诸如SPI闪存设备之类的安全标准存储闪存设备能够实现用于安全存储的数据的重放保护。本发明的实施例利用闪存控制器，闪存设备，唯一设备密钥和HMAC密钥逻辑来为各种组件创建安全的执行环境。

3. 发明申请

US20140297922A1 METHOD AND APPARATUS FOR MANAGING SERIAL PERIPHERAL INTERFACE (SPI) FLASH 审中-公开
标题翻译：用于管理串行外围接口（SPI）闪存的方法和装置
公开(公告)号：US20140297922A1
公开(公告)日：2014-10-02
申请号：US13853429
申请日：2013-03-29
申请人： Nitin V. Sarangdhar , John J. Vranich , Kirk D. Brannock , Steven Dennison
发明人： Nitin V. Sarangdhar , John J. Vranich , Kirk D. Brannock , Steven Dennison
IPC分类号： G06F12/02
CPC分类号： G06F13/16
摘要： A system for communicating with a flash device includes: a controller configured for communicating with the flash device, the controller including logic for classifying a command to the flash device as one of safe and unsafe and communicating each safe command. Methods and a computer program product and a computing system are disclosed.
摘要翻译：一种用于与闪存装置进行通信的系统包括：被配置为与闪存装置进行通信的控制器，所述控制器包括用于将闪存装置的命令分类为安全且不安全的命令的逻辑，并且传达每个安全命令。公开了方法和计算机程序产品和计算系统。

4. 发明申请

US20170181248A1 INFRARED LIGHT EMITTING DIODE CONTROL CIRCUIT 有权
公开(公告)号：US20170181248A1
公开(公告)日：2017-06-22
申请号：US14971525
申请日：2015-12-16
申请人： Nitin V. Sarangdhar , Victoria C. Moore , Kumar N. Dwarakanath
发明人： Nitin V. Sarangdhar , Victoria C. Moore , Kumar N. Dwarakanath
IPC分类号： H05B37/02 , H05B33/08 , H04N5/33 , G06F21/32 , G08B5/36 , G08B21/18
CPC分类号： H05B37/0227 , G06F21/32 , G06F21/82 , G08B5/36 , G08B21/182 , H04N5/33 , H05B33/0842 , H05B37/0281 , Y02B20/42
摘要： Disclosed in some examples are devices, methods, and machine-readable mediums for reliable control of IR LEDs. In some examples, a microcontroller running firmware controls whether the LED is activated or not by use of a disable signal. The microcontroller enables or disables the operation of the LED based upon a user's proximity to the LED, a watchdog timer, and a confirmation that only trusted software is executing.

5. 发明申请

US20170177846A1 PRIVACY PROTECTED INPUT-OUTPUT PORT CONTROL 有权
公开(公告)号：US20170177846A1
公开(公告)日：2017-06-22
申请号：US14978578
申请日：2015-12-22
申请人： Nitin V. Sarangdhar , Raul Gutierrez
发明人： Nitin V. Sarangdhar , Raul Gutierrez
IPC分类号： G06F21/32 , G06F21/62
CPC分类号： G06F21/32 , G06F21/62
摘要： Systems and techniques for privacy protected input-output port control are described herein. In an example, an indication may be obtained that a protected port is disabled. A set of application attributes stored in a secure memory location may be compared to a set of attested application attributes to create a verification flag. At least one port attribute of the protected port may be obtained based on the verification flag. The protected port may be enabled using the at least one port attribute. Other examples, for controlling an input-output port using computer firmware and trusted execution techniques are further disclosed.

6. 发明申请

US20160180095A1 MEASURED BOOT CAPABILITY 审中-公开
标题翻译：测量引导能力
公开(公告)号：US20160180095A1
公开(公告)日：2016-06-23
申请号：US14581275
申请日：2014-12-23
申请人： Nitin V. Sarangdhar
发明人： Nitin V. Sarangdhar
IPC分类号： G06F21/57
CPC分类号： G06F21/575 , G06F11/1417 , G06F21/57 , G06F21/572
摘要： A package with a processing device and integrated cryptographic firmware is described. The package includes a processing device including a processing module to execute a system management mode and a non-volatile memory storing cryptographic firmware to execute one or more cryptographic functions in the system management mode.
摘要翻译：描述了具有处理设备和集成密码固件的包。该包装包括处理装置，其包括执行系统管理模式的处理模块和存储加密固件的非易失性存储器，以在系统管理模式下执行一个或多个密码功能。

7. 发明申请

US20140053262A1 Secure Display for Secure Transactions 审中-公开
标题翻译：安全交易的安全显示
公开(公告)号：US20140053262A1
公开(公告)日：2014-02-20
申请号：US13994839
申请日：2011-09-30
申请人： Nitin V. Sarangdhar , Satyanarayana Avadhanam , Srikanth Kambhatla
发明人： Nitin V. Sarangdhar , Satyanarayana Avadhanam , Srikanth Kambhatla
IPC分类号： H04L29/06
CPC分类号： H04L63/145 , G06F3/14 , G06F9/451 , G06F21/84 , G09G5/14 , G09G2340/14 , G09G2358/00 , G09G2380/00
摘要： A platform may use a central processing unit to run an operating system. Independently of the operating system, in the central processing unit, a hardware controller, such as a manageability engine, may be used to control which window is on the top of the Z-order and thereby control which window is displayed to the user. As a result, in some embodiments, the hardware controller can prevent an interloper or malware from interjecting an illegitimate window over a legitimate window that the user actually desired to access. In addition, a hardware indicator may be provided to assure the user when an accessed website is legitimate.
摘要翻译：平台可以使用中央处理单元来运行操作系统。与操作系统无关的是，在中央处理单元中，可以使用诸如可管理引擎的硬件控制器来控制哪个窗口位于Z顺序的顶部，从而控制向用户显示哪个窗口。结果，在一些实施例中，硬件控制器可以防止中间件或恶意软件在用户实际希望访问的合法窗口上插入非法窗口。此外，可以提供硬件指示符以确保用户何时访问的网站是合法的。

8. 发明授权

US06463554B1 Bus patcher 失效
标题翻译：巴士补丁
公开(公告)号：US06463554B1
公开(公告)日：2002-10-08
申请号：US09156179
申请日：1998-09-17
申请人： Gerald A Budelman , William A. Hobbs , Stephen J. Peters , Tsvika Kurts , Nitin V. Sarangdhar , Kenneth B. Oliver
发明人： Gerald A Budelman , William A. Hobbs , Stephen J. Peters , Tsvika Kurts , Nitin V. Sarangdhar , Kenneth B. Oliver
IPC分类号： G06F1100
CPC分类号： G06F11/349 , G06F11/004 , G06F11/221 , G06F11/25 , G06F2201/88 , H04L41/0631 , H04L43/0811 , H04L43/12
摘要： An apparatus including a protocol watcher adapted for use with a bus, a state machine adapted to detect known bug signatures on the bus, and a perturber adapted to intervene on the bus to prevent occurrence of bugs having those signatures. A system utilizing such includes a bus, a first agent coupled to the bus, a second agent coupled to the bus for communicating to the first agent according to a bus protocol, and the bus patcher coupled to the bus for monitoring a communication from the second agent to the first agent to identify an event which would cause an error in the apparatus, and for modifying the communication such that the event is avoided. Any of the protocol watcher, state machine, and/or perturber may be programmable.
摘要翻译：一种包括适于与总线一起使用的协议观察器的装置，适用于检测总线上的已知错误签名的状态机，以及适用于在总线上干预以防止发生具有这些签名的错误的扰码器。一种使用这种系统的系统包括总线，耦合到总线的第一代理，耦合到总线的第二代理，用于根据总线协议与第一代理进行通信，并且总线修补器耦合到总线，用于监视来自第二个代理到第一代理以识别将导致设备中的错误的事件，以及用于修改通信，使得避免事件。任何协议监视器，状态机和/或监听器都可以是可编程的。

9. 发明授权

US5937171A Method and apparatus for performing deferred transactions 失效
标题翻译：执行延期交易的方法和装置
公开(公告)号：US5937171A
公开(公告)日：1999-08-10
申请号：US669101
申请日：1996-06-26
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams
IPC分类号： G06F13/36 , G06F13/368 , G06F13/37 , G06F13/42 , H04L12/417 , G06F13/14
CPC分类号： G06F13/37 , G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：在计算机系统的总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

10. 发明授权

US5751995A Apparatus and method of maintaining processor ordering in a multiprocessor system which includes one or more processors that execute instructions speculatively 失效
标题翻译：在包括执行指令的一个或多个处理器的多处理器系统中维持处理器排序的装置和方法
公开(公告)号：US5751995A
公开(公告)日：1998-05-12
申请号：US591224
申请日：1996-01-18
申请人： Nitin V. Sarangdhar
发明人： Nitin V. Sarangdhar
IPC分类号： G06F9/38 , G06F9/46 , G06F12/08
CPC分类号： G06F9/52 , G06F12/0831 , G06F9/3834
摘要： In a computer system having a plurality of processors, an apparatus and method for maintaining processor ordering associated with read and write operations of these processors. When data from a producer processor is initially retired, it is stored in a FIFO buffer internal to that processor. If that processor subsequently wishes access to that data, the data is retrieved from and stored back to the FIFO. The data temporarily stored in the FIFO is used to update a main memory shared by the plurality of processors. This update function occurs only after the data has been globally observed in order to guarantee that if any other processor in the system reads data from the main memory, it will obtain an updated version of that data. This ensures that the processor ordering is maintained with respect to the multiple processors residing within the computer system.
摘要翻译：在具有多个处理器的计算机系统中，用于维持与这些处理器的读取和写入操作相关联的处理器排序的装置和方法。当来自生产者处理器的数据最初被退出时，它被存储在该处理器内部的FIFO缓冲器中。如果该处理器随后希望访问该数据，则从数据检索并将其存回FIFO。临时存储在FIFO中的数据用于更新由多个处理器共享的主存储器。该更新功能仅在全局观察数据之后才能发生，以保证系统中任何其他处理器从主存储器读取数据时，将获得该数据的更新版本。这确保了相对于驻留在计算机系统内的多个处理器来维护处理器排序。

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