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    • 6. 发明授权
    • Liner property improvement
    • 班轮物业改善
    • US08617989B2
    • 2013-12-31
    • US13451207
    • 2012-04-19
    • Kedar SapreManuel HernandezLei Luo
    • Kedar SapreManuel HernandezLei Luo
    • H01L21/316H01L23/538
    • H01L21/768H01L21/76831H01L21/76898H01L23/481H01L2924/0002H01L2924/00
    • Methods of forming a dielectric liner layer on a semiconductor substrate are described. The method may include flowing a phosphorus-containing precursor with a silicon-containing precursor and an oxygen-containing precursor over the substrate to deposit a dielectric material. The dielectric material may be deposited along a field region and within at least one via on the substrate having a depth of at least 1 μm. The method may also include forming a liner layer within the via with the dielectric material. The liner may include a silicon oxide doped with phosphorus, and the thickness of the liner layer at an upper portion of the via sidewall may be less than about 5 times the thickness of the liner layer at a lower portion of the via sidewall.
    • 描述在半导体衬底上形成电介质衬垫层的方法。 该方法可以包括使含磷前体和含氧前体在衬底上流动以沉积介电材料。 电介质材料可以沿着场区域并且在至少一个具有至少1um的深度的衬底上的至少一个通孔内沉积。 该方法还可以包括在电介质材料的通路内形成衬里层。 衬垫可以包括掺杂有磷的氧化硅,并且通孔侧壁的上部处的衬垫层的厚度可以小于通孔侧壁的下部处的衬垫层的厚度的约5倍。
    • 7. 发明授权
    • Conformality of oxide layers along sidewalls of deep vias
    • 深层通孔侧壁氧化层的一致性
    • US08404583B2
    • 2013-03-26
    • US13035034
    • 2011-02-25
    • Zhong Qiang HuaManuel A. HernandezLei LuoKedar Sapre
    • Zhong Qiang HuaManuel A. HernandezLei LuoKedar Sapre
    • H01L21/44H01L21/31H01L21/469
    • H01L21/76898
    • A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 μm from a top surface of the nitride layer and an opening of less than about 10 μm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450° C., where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer.
    • 在半导体衬底中的通孔侧壁改善氧化物层的保形性的方法包括在半导体衬底的上表面上形成氮化物层,并形成延伸穿过氮化物层并进入半导体衬底的通孔。 通孔可以具有距离氮化物层的顶表面至少约50μm的深度和在氮化物层的顶表面处的小于约10μm的开口。 该方法还包括在氮化物层上并沿着通孔的侧壁和底部形成氧化物层。 可以在小于约450℃的温度下使用热化学气相沉积(CVD)工艺形成氧化物层,其中通孔底部的氧化物层的厚度为厚度的至少约50% 在氮化物层的顶表面处的氧化物层。
    • 9. 发明申请
    • CONFORMALITY OF OXIDE LAYERS ALONG SIDEWALLS OF DEEP VIAS
    • 深层六角形氧化层的一致性
    • US20110223760A1
    • 2011-09-15
    • US13035034
    • 2011-02-25
    • Zhong Qiang HuaManuel A. HernandezLei LuoKedar Sapre
    • Zhong Qiang HuaManuel A. HernandezLei LuoKedar Sapre
    • H01L21/768
    • H01L21/76898
    • A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 μm from a top surface of the nitride layer and an opening of less than about 10 μm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450° C., where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer.
    • 在半导体衬底中的通孔侧壁改善氧化物层的保形性的方法包括在半导体衬底的上表面上形成氮化物层,并形成延伸穿过氮化物层并进入半导体衬底的通孔。 通孔可以具有距离氮化物层的顶表面至少约50μm的深度和在氮化物层的顶表面处的小于约10μm的开口。 该方法还包括在氮化物层上并沿着通孔的侧壁和底部形成氧化物层。 可以在小于约450℃的温度下使用热化学气相沉积(CVD)工艺形成氧化物层,其中通孔底部的氧化物层的厚度为厚度的至少约50% 在氮化物层的顶表面处的氧化物层。
    • 10. 发明授权
    • Silicon-ozone CVD with reduced pattern loading using incubation period deposition
    • 硅 - 臭氧CVD,使用潜伏期沉积减少图案负载
    • US07994019B1
    • 2011-08-09
    • US12891149
    • 2010-09-27
    • Sasha KweskinPaul Edward GeeShankar VenkataramanKedar Sapre
    • Sasha KweskinPaul Edward GeeShankar VenkataramanKedar Sapre
    • H01L21/00
    • H01L21/02164C23C16/401C23C16/45523H01L21/0228
    • Aspects of the disclosure pertain to methods of depositing conformal silicon oxide layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface having heterogeneous materials and/or a heterogeneous pattern density distribution. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on underlying material and pattern density while still being suitable for non-sacrificial applications. Reduction in dependence on pattern density is achieved by terminating deposition near the end of an incubation period. Multiple deposition cycles may be conducted in series since the beneficial nature of the incubation period may repeat after a pause in deposition.
    • 本公开的方面涉及在图案化衬底上沉积保形氧化硅层的方法。 在实施例中,通过将含硅前体和臭氧流入处理室来沉积电介质层,使得跨越具有异质材料的图案化衬底表面和/或异质图案密度分布实现相对均匀的介电生长速率。 根据实施例生长的电介质层的沉积可以降低对下层材料和图案密度的依赖性,同时仍然适用于非牺牲应用。 依靠图案密度的减少是通过在潜伏期结束时终止沉积来实现的。 多个沉积循环可以串联进行,因为在沉积停顿之后潜伏期的有益特性可以重复。