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1. 发明申请

US20060119493A1 Transmitter for wireless applications incorporation spectral emission shaping sigma delta modulator 有权
标题翻译：用于无线应用的发射机并入光谱发射整形Σ-Δ调制器
公开(公告)号：US20060119493A1
公开(公告)日：2006-06-08
申请号：US11297524
申请日：2005-12-07
申请人： Nir Tal , Sameh Rezeg , Robert Staszewski , Oren Eliezer , Ofer Friedman
发明人： Nir Tal , Sameh Rezeg , Robert Staszewski , Oren Eliezer , Ofer Friedman
IPC分类号： H03M3/00
CPC分类号： H03M7/3017 , H03M7/3022 , H03M7/3042
摘要： A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.
摘要翻译：一种采用具有噪声传递函数的Σ-Δ调制器的发射机，其适于在至少一个感兴趣的频带之外移位量化噪声。提出了一种用于合成单环Σ-Δ调制器中的控制器的技术，使得噪声传递函数可以从满足某些条件的函数族中任意选择。使用新颖的调制器设计技术，支持极坐标和笛卡尔（即正交）发射机结构。呈现采用极性发射调制的发射机，其对数字控制的功率放大器的频谱发射进行整形，使得它们在一个或多个期望的频带中显着且充分衰减。类似地，呈现采用笛卡尔发射调制的发射机，其对混合功率放大器的频谱发射进行整形，使得它们在一个或多个期望的频带中显着且充分衰减。

2. 发明授权

US07460499B2 Modulation noise estimation mechanism 有权
标题翻译：调制噪声估计机制
公开(公告)号：US07460499B2
公开(公告)日：2008-12-02
申请号：US10758913
申请日：2004-01-16
申请人： Oren Eliezer , Bogdan Staszewski , Ofer Friedman
发明人： Oren Eliezer , Bogdan Staszewski , Ofer Friedman
IPC分类号： H04B3/20
CPC分类号： H03C3/0991 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L2207/50
摘要： An on-chip reduced complexity modulation noise estimation mechanism for performing nonlinear signal processing to analyze modulation noise to determine whether a semiconductor device under test complies with the performance criteria set by specifications or a standard corresponding thereto. When used in a two-point transmitter modulation architecture, the mechanism relies on the fact that the noise statistics at the output of the transmitter can be determined by observing the phase error output of the phase detector within the phase locked loop. In the digital embodiment of the mechanism, the phase error signal is compared to a configurable threshold value to generate an exception event. If the number of exception events exceeds a configurable max_fail value after comparisons of a configurable number of phase error samples, the test fails. A pass/fail signal is output reflecting the result of the test. The test comprises a configurable number of test samples to permit flexibility in the tradeoff between the time required to complete the test versus the statistical reliability of the test result, i.e. the probability of it correctly determining whether the tested device complies with target specifications.
摘要翻译：一种用于执行非线性信号处理以分析调制噪声以确定被测半导体器件是否符合由规范或相应的标准设置的性能标准的片上缩减复杂度调制噪声估计机制。当用于两点发射机调制架构时，该机制依赖于以下事实：可以通过观察锁相环内的相位检测器的相位误差输出来确定发射机输出端的噪声统计。在该机构的数字实施例中，将相位误差信号与可配置的阈值进行比较以产生异常事件。如果在比较可配置数量的相位误差样本之后异常事件的数量超过可配置的max_fail值，则测试失败。输出反映测试结果的通过/失败信号。该测试包括可配置数量的测试样本，以允许在完成测试所需的时间与测试结果的统计可靠性之间进行权衡的灵活性，即，其正确确定被测试设备是否符合目标规范的概率。

3. 发明申请

US20070103240A1 Gain Calibration of a Digital Controlled Oscillator 有权
标题翻译：数字控制振荡器的增益校准
公开(公告)号：US20070103240A1
公开(公告)日：2007-05-10
申请号：US11619529
申请日：2007-01-03
申请人： Robert Staszewski , Gennady Feygin , Oren Eliezer , Dirk Leipold
发明人： Robert Staszewski , Gennady Feygin , Oren Eliezer , Dirk Leipold
IPC分类号： H03L7/00
CPC分类号： H03L7/0991 , H03L7/085 , H03L2207/50
摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
摘要翻译：一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。然后将梯度缩放并添加到DCO增益乘数的当前值。

4. 发明申请

US20060132431A1 Multi-function digital device as a human-input-device for a computer 审中-公开
标题翻译：多功能数字设备作为计算机的人机输入设备
公开(公告)号：US20060132431A1
公开(公告)日：2006-06-22
申请号：US11015562
申请日：2004-12-17
申请人： Oren Eliezer , Carl Panasik , John Wallberg , Robert Staszewski
发明人： Oren Eliezer , Carl Panasik , John Wallberg , Robert Staszewski
IPC分类号： G09G5/00
CPC分类号： G06F3/0317 , G06F1/1616 , G06F1/1626 , G06F1/1684 , G06F1/1686 , G06F1/169 , G06F1/1694 , G06F1/1698 , G06F3/0354 , G06F3/03547 , G06F3/04886 , H04M2250/52 , H04W52/0267 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164 , Y02D70/23
摘要： System and method for interfacing with a digital computer using a multi-function device. A preferred embodiment comprises a multi-function device comprising a controller configured to process information and regulate operations of the multi-function device, a sensor coupled to the controller, the sensor configured to capture information in a movement of the multi-function device or a movement of an object applied to the multi-function device and to provide the information to the controller, wherein the information is used to determine movement information. The multi-function device further comprises a radio frequency circuit also coupled to the controller, the radio frequency circuit is configured to exchange information with other devices via a plurality of communications networks, wherein one of the other devices is a computer and the information shared is movement information from the multi-function device.
摘要翻译：使用多功能设备与数字计算机进行接口的系统和方法。优选实施例包括多功能设备，其包括被配置为处理信息并调节多功能设备的操作的控制器，耦合到控制器的传感器，被配置为捕获多功能设备的移动中的信息或应用于多功能装置的物体的移动以及将信息提供给控制器，其中所述信息用于确定移动信息。多功能设备还包括还耦合到控制器的射频电路，射频电路被配置为经由多个通信网络与其他设备交换信息，其中其他设备之一是计算机，并且共享的信息是来自多功能设备的运动信息。

5. 发明申请

US20060038710A1 Hybrid polar/cartesian digital modulator 有权
公开(公告)号：US20060038710A1
公开(公告)日：2006-02-23
申请号：US11203019
申请日：2005-08-11
申请人： Robert Staszewski , Oren Eliezer
发明人： Robert Staszewski , Oren Eliezer
IPC分类号： H03M3/00
CPC分类号： H03F3/24 , H03F2200/331 , H03M1/005 , H03M1/68 , H03M1/747 , H03M3/50 , H03M7/3022 , H04L27/361
摘要： A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all digital phase locked loop (ADPLL) that features a wideband frequency modulation capability and a digitally controlled power amplifier (DPA) that features interpolation between 90 degree spaced quadrature phases. This structure is capable of performing either a polar operation or a Cartesian operation and can dynamically switch between them depending on the instantaneous value of a metric measured by a thresholder/router. In this manner, the disadvantages of each modulation technique are avoided while the benefits of each are exploited.

6. 发明申请

US20060291589A1 Method and apparatus for a fully digital quadrature modulator 有权
标题翻译：全数字正交调制器的方法和装置
公开(公告)号：US20060291589A1
公开(公告)日：2006-12-28
申请号：US11203504
申请日：2005-08-11
申请人： Oren Eliezer , Francis Cruise , Robert Staszewski , Jaimin Mehta
发明人： Oren Eliezer , Francis Cruise , Robert Staszewski , Jaimin Mehta
IPC分类号： H04L27/12
CPC分类号： H03F3/24 , H03C3/40 , H03C5/00 , H03F2200/324 , H03F2200/331 , H03F2200/336 , H04K1/02 , H04L27/04 , H04L27/2092 , H04L27/365
摘要： A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.
摘要翻译：一种用于复调制器的全数字正交架构的新型装置和方法。复调制器可以替代现有的现有技术的模拟正交调制器结构和基于数字极坐标（r，θ）的那些。调制器有效地作为复数数模转换器工作，其中数字输入以笛卡尔形式给出，即I和Q表示复数I + jQ，而输出是具有对应幅度和相移的调制RF信号。相移相对于由本地振荡器指定的参考相位，本地振荡器也被输入到转换器/调制器。提供了包括具有双I和Q晶体管阵列的调制器，单个共享I / Q晶体管阵列，具有单端和差分输出的调制器以及具有单极性和双极性时钟和I / Q数据信号的调制器的几个实施例。

7. 发明申请

US20060033582A1 Gain calibration of a digital controlled oscillator 有权
标题翻译：增益数字控制振荡器的校准
公开(公告)号：US20060033582A1
公开(公告)日：2006-02-16
申请号：US11149859
申请日：2005-06-10
申请人： Robert Staszewski , Gennady Feygin , Oren Eliezer , Dirk Leipold
发明人： Robert Staszewski , Gennady Feygin , Oren Eliezer , Dirk Leipold
IPC分类号： H03L7/00
CPC分类号： H03L7/0991 , H03L7/085 , H03L2207/50
摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
摘要翻译：一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。然后将梯度缩放并添加到DCO增益乘数的当前值。

8. 发明授权

US07958408B2 On-chip receiver sensitivity test mechanism 有权
标题翻译：片上接收机灵敏度测试机制
公开(公告)号：US07958408B2
公开(公告)日：2011-06-07
申请号：US11835274
申请日：2007-08-07
申请人： Elida Isabel de Obaldia , Dirk Leipold , Oren Eliezer , Ran Katz , Bogdan Staszewski
发明人： Elida Isabel de Obaldia , Dirk Leipold , Oren Eliezer , Ran Katz , Bogdan Staszewski
IPC分类号： H04B17/00
CPC分类号： H04B17/0085 , G01R31/2822 , H04B17/29 , H04L1/24
摘要： An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillators to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated. The BER reading is used either externally or by an on-chip processor or controller to establish a pass/fail indication for the chip.
摘要翻译：用于集成RF发射机的片上接收机灵敏度测试机构，其中发射机和接收机共享相同的振荡器。该机构避免了使用具有内置调制能力的昂贵的RF信号发生器测试设备的需要，并且允许使用非常低成本的外部RF测试设备。本发明利用已经存在于收发器中的电路，即调制电路和本地振荡器来执行灵敏度测试。片上LO用于产生调制测试信号，否则将需要由具有调制能力的昂贵的外部RF测试设备提供。调制的LO信号与外部产生的未调制的CW RF信号混合以在IF处产生调制信号，随后由接收器链的其余部分处理。恢复的数据位使用片上BER计或计数器进行比较，产生BER读数。 BER读取在外部使用或由片上处理器或控制器用于建立芯片的通过/失败指示。

9. 发明授权

US07035750B2 On-chip test mechanism for transceiver power amplifier and oscillator frequency 有权
标题翻译：收发器功率放大器和振荡器频率的片上测试机制
公开(公告)号：US07035750B2
公开(公告)日：2006-04-25
申请号：US10759912
申请日：2004-01-16
申请人： Elida Isabel de Obaldia , Chih-Ming Hung , Dirk Leipold , Oren Eliezer
发明人： Elida Isabel de Obaldia , Chih-Ming Hung , Dirk Leipold , Oren Eliezer
IPC分类号： G01R31/00
CPC分类号： H03K5/08 , H04B17/102 , H04B17/16 , H04B17/20
摘要： An on-chip test mechanism for transceiver power amplifier and oscillator frequency for use with the transmitter portion of an integrated RF transceiver. The RF output from the power amplifier in the transmitter is input to a built-in dedicated analog comparator having a configurable threshold. The threshold is adjusted to a predetermined level at which crossings start to occur at the comparator output. The comparator outputs pulses only if the power amplifier output is above a minimum configurable level. The comparator output is input to a frequency divider whose frequency output is tested by a low cost external tester to determine the actual RF frequency thereby confirming generation of the correct oscillator frequency and that the amplitude of the signal at the output of the power amplifier is sufficiently high for the configurable threshold level to be exceeded, thereby determining the compliance of the output power with its defined specifications.
摘要翻译：用于收发器功率放大器和振荡器频率的片上测试机制，用于集成RF收发器的发射器部分。发射机功率放大器的RF输出被输入到具有可配置阈值的内置专用模拟比较器。阈值被调整到在比较器输出处开始发生交叉的预定电平。仅当功率放大器输出高于最小可配置电平时，比较器才会输出脉冲。比较器输出被输入到分频器，其频率输出由低成本外部测试仪测试以确定实际RF频率，从而确认产生正确的振荡器频率，并且功率放大器输出端的信号幅度足够可以超过可配置的阈值电平，从而确定输出功率与其规定的规格的一致性。

10. 发明申请

US20050088215A1 ADJUSTMENT OF AMPLITUDE AND DC OFFSETS IN A DIGITAL RECEIVER 有权
标题翻译：数字接收机中的幅度和直流偏移的调整
公开(公告)号：US20050088215A1
公开(公告)日：2005-04-28
申请号：US10690683
申请日：2003-10-22
申请人： Udi Suissa , Oren Eliezer , Ran Katz
发明人： Udi Suissa , Oren Eliezer , Ran Katz
IPC分类号： H04L25/06 , H03K5/153
CPC分类号： H04L25/061
摘要： A nonlinear adaptive mechanism for amplitude adjustment and DC estimation and compensation for use in a digital receiver such as a Bluetooth GFSK receiver. The mechanism uses a feed-forward technique that can be used in a multi-stage scheme to perform both DC compensation and amplitude adjustment of an input signal for use by subsequent processing stages. In a first stage, coarse DC offset compensation is performed and the offset estimates generated are subsequently frozen. In a second stage, the incoming signal with the DC offset subtracted from it, is then scaled into a narrow predefined range of amplitudes using a scaling mechanism that works with gains and attenuations that are powers of two in order to simplify implementation. In a third stage, the scaled compensated signal is then injected again into the same DC estimation mechanism, which was previously used for DC compensation in the first stage, for further DC offset estimation and compensation (i.e. fine DC estimation and compensation).
摘要翻译：用于幅度调整和DC估计和补偿的非线性自适应机制，用于诸如蓝牙GFSK接收机的数字接收机中。该机制使用可以在多级方案中使用的前馈技术来执行输入信号的DC补偿和幅度调整，以供后续处理阶段使用。在第一阶段，执行粗直流偏移补偿，随后产生的偏移估计被冻结。在第二阶段中，使用从其中减去DC偏移的输入信号被缩放到窄的预定范围的幅度，使用缩放机制，其以增益和衰减为功效，以便简化实现。在第三阶段，再次将经缩放的经补偿的信号注入到先前用于第一级DC补偿的同一直流估计机构中，用于进一步的直流偏移估计和补偿（即精细直流估计和补偿）。

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