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    • 1. 发明授权
    • On-chip test mechanism for transceiver power amplifier and oscillator frequency
    • 收发器功率放大器和振荡器频率的片上测试机制
    • US07035750B2
    • 2006-04-25
    • US10759912
    • 2004-01-16
    • Elida Isabel de ObaldiaChih-Ming HungDirk LeipoldOren Eliezer
    • Elida Isabel de ObaldiaChih-Ming HungDirk LeipoldOren Eliezer
    • G01R31/00
    • H03K5/08H04B17/102H04B17/16H04B17/20
    • An on-chip test mechanism for transceiver power amplifier and oscillator frequency for use with the transmitter portion of an integrated RF transceiver. The RF output from the power amplifier in the transmitter is input to a built-in dedicated analog comparator having a configurable threshold. The threshold is adjusted to a predetermined level at which crossings start to occur at the comparator output. The comparator outputs pulses only if the power amplifier output is above a minimum configurable level. The comparator output is input to a frequency divider whose frequency output is tested by a low cost external tester to determine the actual RF frequency thereby confirming generation of the correct oscillator frequency and that the amplitude of the signal at the output of the power amplifier is sufficiently high for the configurable threshold level to be exceeded, thereby determining the compliance of the output power with its defined specifications.
    • 用于收发器功率放大器和振荡器频率的片上测试机制,用于集成RF收发器的发射器部分。 发射机功率放大器的RF输出被输入到具有可配置阈值的内置专用模拟比较器。 阈值被调整到在比较器输出处开始发生交叉的预定电平。 仅当功率放大器输出高于最小可配置电平时,比较器才会输出脉冲。 比较器输出被输入到分频器,其频率输出由低成本外部测试仪测试以确定实际RF频率,从而确认产生正确的振荡器频率,并且功率放大器输出端的信号幅度足够 可以超过可配置的阈值电平,从而确定输出功率与其规定的规格的一致性。
    • 5. 发明申请
    • Low noise high isolation transmit buffer gain control mechanism
    • 低噪声高隔离传输缓冲器增益控制机制
    • US20050287967A1
    • 2005-12-29
    • US11115815
    • 2005-04-26
    • Chih-Ming HungFrancis CruiseDirk LeipoldRobert Staszewski
    • Chih-Ming HungFrancis CruiseDirk LeipoldRobert Staszewski
    • H01Q11/12H03F1/32H03F3/191H04B1/04
    • H04B1/0483H03F1/3241H03F1/3294H03F3/191H03F2200/331
    • A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.
    • 一种低噪声,高隔离,全数字发送缓冲增益控制机制的新型设备。 增益控制方案在全数字直接数/频幅度转换器(DRAC)的上下文中呈现,该转换器有效地结合了上变频,I和Q组合,D / A转换,滤波,缓冲和 RF输出幅度控制成单个电路。 发送缓冲器构造为NMOS开关阵列。 每个NMOS开关的控制逻辑包括一个通门型AND门,其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。 通过在CMOS工艺中实现时,通过识别伪E类预功率放大器(PPA)所遭受的损伤来实现功率控制。 首先,阵列的NMOS开关具有大的导通电阻,因此当输入波形为高时,只能从RF扼流圈画出有限的电流。 在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制,并允许控制RF输出功率的全数字方法。
    • 9. 发明授权
    • Negative contributive offset compensation in a transmit buffer utilizing inverse clocking
    • 使用反向时钟的发送缓冲器中的负贡献偏移补偿
    • US07405685B2
    • 2008-07-29
    • US11178993
    • 2005-07-11
    • Sameh S. RezeqDirk LeipoldRobert B. StaszewskiChih-Ming Hung
    • Sameh S. RezeqDirk LeipoldRobert B. StaszewskiChih-Ming Hung
    • H03M3/00
    • H03F1/0205H03F1/3241H03F2200/331H03F2200/375H03M3/356H03M3/50H03M7/3026H03M7/3037H04L27/368
    • A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
    • 一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置,适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。 来自Σ-Δ调制器的正输出的处理方式与负输出不同。 与Σ-Δ调制器中的负输出相关联的反相器被去除,并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。 时钟的非反相版本与正输出一起使用,反向时钟与负输出一起使用。 使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。 结果是具有零偏移的偏移补偿RF输出信号。