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1. 发明授权

US07317630B2 Nonvolatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US07317630B2
公开(公告)日：2008-01-08
申请号：US11182374
申请日：2005-07-15
申请人： Nicola Telecco , Vijay P. Adusumilli , Anil Gupta , Edward Hui , Steven J. Schumann
发明人： Nicola Telecco , Vijay P. Adusumilli , Anil Gupta , Edward Hui , Steven J. Schumann
IPC分类号： G11C5/06
CPC分类号： G11C7/10 , H01L2224/05553 , H01L2224/48137 , H01L2224/49175
摘要： A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.
摘要翻译：非易失性存储装置包括单独的控制器电路和存储器电路。控制器电路制造在第一集成电路芯片上。控制器电路包括多个电荷泵电路，系统接口逻辑电路，存储器控制逻辑电路和一个或多个模拟电路。存储器电路制造在第二集成电路芯片上，并且包括列解码器，行解码器，控制寄存器和数据寄存器。存储器控制器接口区域包括第一集成电路芯片上的第一多个管芯接合焊盘和第二集成电路芯片上的第二多个管芯接合焊盘，使得第一和第二集成电路芯片可以芯片结合在一起。单个控制器电路可以与多个存储器电路接口，从而进一步降低总体成本，因为每个存储器电路不需要专用控制器电路。

2. 发明授权

US06359810B1 Page mode erase in a flash memory array 有权
标题翻译：页面模式在闪存阵列中擦除
公开(公告)号：US06359810B1
公开(公告)日：2002-03-19
申请号：US09542434
申请日：2000-04-04
申请人： Anil Gupta , Steven J. Schumann
发明人： Anil Gupta , Steven J. Schumann
IPC分类号： G11C1604
CPC分类号： G11C5/147 , G11C16/16
摘要： In a sector in a flash memory array PAGE ERASE and MULTIPLE PAGE ERASE modes of operation are provided. In the PAGE ERASE and MULTIPLE PAGE ERASE modes of operation, a preferred tunneling potential of approximately −10 Volts is applied to the gates of the flash memory cells on the row or rows being selected for erasure, and the bitlines connected to the drains of the flash memory cells are driven to a preferred voltage of approximately 6.5 Volts. To reduce the unintended erasure of memory cells in rows other than the selected row or rows, a preferred bias voltage of approximately 1 to 2 Volts is applied to the gates of all the flash memory cells in the rows other than the selected row or rows.
摘要翻译：在闪存阵列的扇区中，提供了PAGE ERASE和MULTIPLE PAGE ERASE操作模式。在PAGE ERASE和MULTIPLE PAGE ERASE操作模式下，将大约-10伏特的优选隧道电位施加到被选择用于擦除的行或行上的闪存单元的栅极，并且连接到闪存单元被驱动到大约6.5伏的优选电压。为了减少存储器单元在非所选择的行或行以外的行中的非预期擦除，将大约1至2伏特的优选偏置电压施加到除所选择的行或行之外的行中的所有快闪存储器单元的栅极。

3. 发明授权

US5822245A Dual buffer flash memory architecture with multiple operating modes 失效
公开(公告)号：US5822245A
公开(公告)日：1998-10-13
申请号：US824175
申请日：1997-03-26
申请人： Anil Gupta , Steven J. Schumann
发明人： Anil Gupta , Steven J. Schumann
IPC分类号： G11C7/10 , G11C16/10 , G11C16/26 , G11C11/34
CPC分类号： G11C7/1045 , G11C16/10 , G11C16/26 , G11C16/3431
摘要： A flash memory array architecture comprising a flash memory array, first and second memory buffer, and I/O interface circuit which has several operating modes which permit data to be read from the flash memory array, several operating modes which permit data to be programmed into the flash memory array, and a mode for rewriting the data in the flash memory array.In the four read modes, one of the pages stored in the flash memory array is read, the data stored in either of first or second memory buffers is read, the data in one of the pages of data stored in the flash memory array is read and then written into either of first or second memory buffers, the data in one of the pages of data stored in the flash memory array is read and then compared to the data read from either of first or second memory buffers. In the four write modes, data from an input stream is written into a selected first or second memory buffer, one of the pages of data stored in the flash memory array is erased, and then in the same cycle, data in either of first or second memory buffers is written into the erased page in the flash memory array, data in either of first or second memory buffers is written into a previously erased page in the flash memory array, and data from an input stream is written into the selected first or second memory buffer, one of the pages of data stored in the flash memory array is erased, and then in the same cycle, data in either of first or second memory buffers is written into the erased page in the flash memory array. In the auto page rewrite mode, the data in one of the pages of data stored in the flash memory array is read and then written into either of first or second memory buffers. The data stored in the page of the flash memory array just read is erased, and then in the same cycle, the page of data stored in the selected first or second memory buffer is written into the erased page in the flash memory array.

4. 发明授权

US6118705A Page mode erase in a flash memory array 失效
公开(公告)号：US6118705A
公开(公告)日：2000-09-12
申请号：US42244
申请日：1998-03-13
申请人： Anil Gupta , Steven J. Schumann
发明人： Anil Gupta , Steven J. Schumann
IPC分类号： G11C16/02 , G11C11/40 , G11C16/00 , G11C16/04 , G11C16/16
CPC分类号： G11C16/16
摘要： In a sector in a flash memory array PAGE ERASE and MULTIPLE PAGE ERASE modes of operation are provided. In the PAGE ERASE and MULTIPLE PAGE ERASE modes of operation, a preferred tunneling potential of approximately -10 Volts is applied to the gates of the flash memory cells on the row or rows being selected for erasure, and the bitlines connected to the drains of the flash memory cells are driven to a preferred voltage of approximately 6.5 Volts. To reduce the unintended erasure of memory cells in rows other than the selected row or rows, a preferred bias voltage of approximately 1 to 2 Volts is applied to the gates of all the flash memory cells in the rows other than the selected row or rows.

5. 发明授权

US07099226B2 Functional register decoding system for multiple plane operation 失效
标题翻译：功能寄存器解码系统，用于多平面操作
公开(公告)号：US07099226B2
公开(公告)日：2006-08-29
申请号：US10686401
申请日：2003-10-14
申请人： Yolanda Yuan , Jason Guo , Sai K. Tsang , Vikram Kowshik , Steven J. Schumann
发明人： Yolanda Yuan , Jason Guo , Sai K. Tsang , Vikram Kowshik , Steven J. Schumann
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1027 , G11C7/1042 , G11C7/1045
摘要： A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.
摘要翻译：用于多平面存储器的解码系统将对应于不同存储器访问操作的地址信息路由到指定的平面。该系统包括专用于随机访问读取，突发读取，编程，擦除和擦除 - 挂起程序操作的功能寄存器阵列。每个平面的平面选择器块接收所有寄存器的地址输出，平面函数选择逻辑根据指定平面的存储器访问命令控制路由。同一平面内不同类型的同时操作和嵌套操作是可能的。

6. 发明授权

US06940759B2 Group erasing system for flash array with multiple sectors 有权
标题翻译：具有多个扇区的闪存阵列的组擦除系统
公开(公告)号：US06940759B2
公开(公告)日：2005-09-06
申请号：US10685957
申请日：2003-10-14
申请人： Sai K. Tsang , Steven J. Schumann , Fai Ching
发明人： Sai K. Tsang , Steven J. Schumann , Fai Ching
IPC分类号： G11C8/10 , G11C8/12 , G11C11/34 , G11C16/00 , G11C16/16
CPC分类号： G11C16/16 , G11C8/10 , G11C8/12 , G11C16/3477
摘要： A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.
摘要翻译：用于多平面存储器的解码系统将对应于不同存储器访问操作的地址信息路由到指定的平面。该系统包括专用于随机访问读取，突发读取，编程，擦除和擦除 - 挂起程序操作的功能寄存器阵列。每个平面的平面选择器块接收所有寄存器的地址输出，平面函数选择逻辑根据指定平面的存储器访问命令控制路由。同一平面内不同类型的同时操作和嵌套操作是可能的。

7. 发明授权

US07143257B2 Method and apparatus of a smart decoding scheme for fast synchronous read in a memory system 失效
标题翻译：用于在存储器系统中快速同步读取的智能解码方案的方法和装置
公开(公告)号：US07143257B2
公开(公告)日：2006-11-28
申请号：US10686243
申请日：2003-10-14
申请人： Vikram Kowshik , Fai Ching , Steven J. Schumann
发明人： Vikram Kowshik , Fai Ching , Steven J. Schumann
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/4243
摘要： An apparatus and method identify a plurality of words to be read, read these selected words during a clock latency period, and then shift these words out synchronously at an end of the latency period. In another aspect of the present invention, the above method of reading a plurality of words during a clock latency period and shifting them out synchronously after the latency period is facilitated by a two tier column decoder. The two-tier column decoder has two decoders. A first-tier decoder decodes a first group of words to be read during the latency period, and a second-tier decoder decodes subsequent words to be shifted out synchronously during a burst period.
摘要翻译：一种装置和方法识别要读取的多个单词，在时钟等待时段期间读取这些所选择的单词，然后在等待时间周期结束时同步地移出这些单词。在本发明的另一方面，上述在时钟等待时段期间读取多个单词并且在等待时间间隔之后将它们同步地移出的方法由双层列解码器促成。双层列解码器有两个解码器。第一层解码器在等待时段期间解码要读取的第一组字，并且第二层解码器在突发周期期间同步地解码要同步移出的后续字。

8. 发明授权

US5732017A Combined program and data nonvolatile memory with concurrent program-read/data write capability 失效
标题翻译：组合的程序和数据非易失性存储器，具有并行程序读取/数据写入功能
公开(公告)号：US5732017A
公开(公告)日：1998-03-24
申请号：US829378
申请日：1997-03-31
申请人： Steven J. Schumann , Fai Ching , Sai K. Tsang
发明人： Steven J. Schumann , Fai Ching , Sai K. Tsang
IPC分类号： G11C16/02 , G11C11/00 , G11C16/04 , G11C16/10 , G11C16/26 , G11C11/34
CPC分类号： G11C11/005 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory device includes two floating-gate-type memory arrays, e.g. a flash memory intended to be used as a relatively permanent program memory and an E.sup.2 PROM intended to be used as a more frequently updated data memory. A single set of address lines and a single set of data lines are used for both read and write operations for both memory arrays. Address decoding means for accessing an addressed location of a selected memory array includes separate column decoders and data latches for each array, but also includes a shared row decoder common to both arrays. Row address latching circuitry associated with at least the data memory holds a decoded row address for that memory array during a write operation so as to free the shared row decoder for use on one or more concurrent read operations for the other memory array, e.g. the program memory. Data I/O buffer circuitry and sense amplifiers are also shared by both arrays. Control logic, responsive to input control signals selecting one of the memory arrays and selecting a read or write operation, controls the various elements of the device, including address and data latches and select/driver circuitry, to carry out the desired operations.
摘要翻译：非易失性存储器件包括两个浮栅型存储器阵列，例如，旨在用作相对永久的程序存储器的闪存和旨在用作更频繁更新的数据存储器的E2PROM。一组地址线和一组数据线用于两个存储器阵列的读和写操作。用于访问所选择的存储器阵列的寻址位置的地址解码装置包括用于每个阵列的单独的列解码器和数据锁存器，但是还包括两个阵列共用的共享行解码器。与至少数据存储器相关联的行地址锁存电路在写入操作期间保持该存储器阵列的解码行地址，从而释放共享行解码器以用于另一个存储器阵列的一个或多个并行读取操作，例如，程序存储器数据I / O缓冲电路和读出放大器也由两个阵列共享。控制逻辑响应于选择存储器阵列之一并选择读或写操作的输入控制信号，控制设备的各种元件，包括地址和数据锁存器以及选择/驱动器电路，以执行所需的操作。

9. 发明授权

US5094968A Fabricating a narrow width EEPROM with single diffusion electrode formation 失效
标题翻译：制造具有单扩散电极形成的窄宽度EEPROM
公开(公告)号：US5094968A
公开(公告)日：1992-03-10
申请号：US647308
申请日：1991-01-28
申请人： Steven J. Schumann , James C. Hu
发明人： Steven J. Schumann , James C. Hu
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , Y10S148/031 , Y10S148/111
摘要： An EEPROM design featuring narrow linear electrodes including a source, a drain, a thin oxide, channel and floating gate. A pair of linear, opposed field oxide barrier walls form widthwise boundaries of the active structure which can be very closely spaced. The drain electrode, implanted in the substrate, abuts both opposed field oxide lateral walls, but does not extend under either wall. The source, drain and channel are formed in a single implant followed by diffusion after the field oxide barrier walls are formed, but prior to formation of the floating gate. All but opposed field oxide walls in a stripe design. A control gate is disposed over the floating gate. The combination of opposed field oxide barrier walls, a stripe electrode design, and single step implant for electrode formation results in a very compact cell, utilizing a simplified EEPROM process.
摘要翻译：具有窄线性电极的EEPROM设计，包括源极，漏极，薄氧化物，沟道和浮动栅极。一对线性，相对的场氧化物阻挡壁形成活动结构的横向边界，其可以非常紧密地间隔开。植入衬底中的漏电极邻接两个相对的场氧化物侧壁，但不延伸到两壁之下。在形成场氧化物阻挡壁之后但在形成浮栅之前，将源极，漏极和沟道形成为单个注入，随后扩散。在条纹设计中所有但不是相反的场氧化物墙壁。控制栅极设置在浮动栅极上。相对的场氧化物阻挡壁，条状电极设计和用于电极形成的单步注入的组合导致使用简化的EEPROM工艺的非常紧凑的电池。

10. 发明授权

US5086325A Narrow width EEPROM with single diffusion electrode formation 失效
标题翻译：窄宽度EEPROM，单扩散电极形成
公开(公告)号：US5086325A
公开(公告)日：1992-02-04
申请号：US616460
申请日：1990-11-21
申请人： Steven J. Schumann , James C. Hu
发明人： Steven J. Schumann , James C. Hu
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7883
摘要： An EEPROM design featuring narrow linear electrodes including a source, a drain, a thin oxide, channel and floating gate. A pair of linear, opposed field oxide barrier walls form widthwise boundaries of the active structure which can be very closely spaced. The drain electrode, implanted in the substrate, abuts both opposed field oxide lateral walls, but does not extend under either wall. The source, drain and channel are formed in a single implant followed by diffusion after the field oxide barrier walls are formed, but prior to formation of the floating gate. All abut opposed field oxide walls in a stripe design. A control gate is disposed over the floating gate. The combination of opposed field oxide barrier walls, a stripe electrode design, and single step implant for electrode formation results in a very compact cell, utilizing a simplified EEPROM process.
摘要翻译：具有窄线性电极的EEPROM设计，包括源极，漏极，薄氧化物，沟道和浮动栅极。一对线性，相对的场氧化物阻挡壁形成活动结构的横向边界，其可以非常紧密地间隔开。植入衬底中的漏电极邻接两个相对的场氧化物侧壁，但不延伸到两壁之下。在形成场氧化物阻挡壁之后但在形成浮栅之前，将源极，漏极和沟道形成为单个注入，随后扩散。在条纹设计中所有邻接的相对的场氧化物壁。控制栅极设置在浮动栅极上。相对的场氧化物阻挡壁，条状电极设计和用于电极形成的单步注入的组合导致使用简化的EEPROM工艺的非常紧凑的电池。

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