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1. 发明授权

US07099226B2 Functional register decoding system for multiple plane operation 失效
标题翻译：功能寄存器解码系统，用于多平面操作
公开(公告)号：US07099226B2
公开(公告)日：2006-08-29
申请号：US10686401
申请日：2003-10-14
申请人： Yolanda Yuan , Jason Guo , Sai K. Tsang , Vikram Kowshik , Steven J. Schumann
发明人： Yolanda Yuan , Jason Guo , Sai K. Tsang , Vikram Kowshik , Steven J. Schumann
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1027 , G11C7/1042 , G11C7/1045
摘要： A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.
摘要翻译：用于多平面存储器的解码系统将对应于不同存储器访问操作的地址信息路由到指定的平面。该系统包括专用于随机访问读取，突发读取，编程，擦除和擦除 - 挂起程序操作的功能寄存器阵列。每个平面的平面选择器块接收所有寄存器的地址输出，平面函数选择逻辑根据指定平面的存储器访问命令控制路由。同一平面内不同类型的同时操作和嵌套操作是可能的。

2. 发明授权

US06940759B2 Group erasing system for flash array with multiple sectors 有权
标题翻译：具有多个扇区的闪存阵列的组擦除系统
公开(公告)号：US06940759B2
公开(公告)日：2005-09-06
申请号：US10685957
申请日：2003-10-14
申请人： Sai K. Tsang , Steven J. Schumann , Fai Ching
发明人： Sai K. Tsang , Steven J. Schumann , Fai Ching
IPC分类号： G11C8/10 , G11C8/12 , G11C11/34 , G11C16/00 , G11C16/16
CPC分类号： G11C16/16 , G11C8/10 , G11C8/12 , G11C16/3477
摘要： A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.
摘要翻译：用于多平面存储器的解码系统将对应于不同存储器访问操作的地址信息路由到指定的平面。该系统包括专用于随机访问读取，突发读取，编程，擦除和擦除 - 挂起程序操作的功能寄存器阵列。每个平面的平面选择器块接收所有寄存器的地址输出，平面函数选择逻辑根据指定平面的存储器访问命令控制路由。同一平面内不同类型的同时操作和嵌套操作是可能的。

3. 发明授权

US5732017A Combined program and data nonvolatile memory with concurrent program-read/data write capability 失效
标题翻译：组合的程序和数据非易失性存储器，具有并行程序读取/数据写入功能
公开(公告)号：US5732017A
公开(公告)日：1998-03-24
申请号：US829378
申请日：1997-03-31
申请人： Steven J. Schumann , Fai Ching , Sai K. Tsang
发明人： Steven J. Schumann , Fai Ching , Sai K. Tsang
IPC分类号： G11C16/02 , G11C11/00 , G11C16/04 , G11C16/10 , G11C16/26 , G11C11/34
CPC分类号： G11C11/005 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory device includes two floating-gate-type memory arrays, e.g. a flash memory intended to be used as a relatively permanent program memory and an E.sup.2 PROM intended to be used as a more frequently updated data memory. A single set of address lines and a single set of data lines are used for both read and write operations for both memory arrays. Address decoding means for accessing an addressed location of a selected memory array includes separate column decoders and data latches for each array, but also includes a shared row decoder common to both arrays. Row address latching circuitry associated with at least the data memory holds a decoded row address for that memory array during a write operation so as to free the shared row decoder for use on one or more concurrent read operations for the other memory array, e.g. the program memory. Data I/O buffer circuitry and sense amplifiers are also shared by both arrays. Control logic, responsive to input control signals selecting one of the memory arrays and selecting a read or write operation, controls the various elements of the device, including address and data latches and select/driver circuitry, to carry out the desired operations.
摘要翻译：非易失性存储器件包括两个浮栅型存储器阵列，例如，旨在用作相对永久的程序存储器的闪存和旨在用作更频繁更新的数据存储器的E2PROM。一组地址线和一组数据线用于两个存储器阵列的读和写操作。用于访问所选择的存储器阵列的寻址位置的地址解码装置包括用于每个阵列的单独的列解码器和数据锁存器，但是还包括两个阵列共用的共享行解码器。与至少数据存储器相关联的行地址锁存电路在写入操作期间保持该存储器阵列的解码行地址，从而释放共享行解码器以用于另一个存储器阵列的一个或多个并行读取操作，例如，程序存储器数据I / O缓冲电路和读出放大器也由两个阵列共享。控制逻辑响应于选择存储器阵列之一并选择读或写操作的输入控制信号，控制设备的各种元件，包括地址和数据锁存器以及选择/驱动器电路，以执行所需的操作。

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